公开(公告)号：US06178518B1

公开(公告)日：2001-01-23

申请号：US09165692

申请日：1998-10-02

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G06F104

CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/225

摘要： A maximum flight time measuring circuit constituted by a first delay circuit for delaying a system clock and controlling its delay time in accordance with a strobe clock from DIMMs and a delayline register circuit for storing a delayed state in the delay circuit, and a second delay circuit are provided. Contents of the delayline register circuit are input to the second delay circuit, which is controlled to generate the same delay as that of the first delay circuit. The output of the second delay circuit is supplied as a data fetch signal to a control buffer for receiving read data DQ from the DIMMs.

摘要翻译： 一种最大飞行时间测量电路，由第一延迟电路构成，用于根据来自DIMM的选通时钟延迟系统时钟并控制其延迟时间;以及延迟线寄存器电路，用于在延迟电路中存储延迟状态;以及第二延迟电路 被提供。 延迟线寄存器电路的内容被输入到第二延迟电路，其被控制以产生与第一延迟电路相同的延迟。 第二延迟电路的输出作为数据提取信号提供给用于从DIMM接收读取数据DQ的控制缓冲器。

公开(公告)号：US6104649A

公开(公告)日：2000-08-15

申请号：US447190

申请日：1999-11-22

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C29/04 ,  G11C7/00 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00

CPC分类号： G11C29/785 ,  G11C29/808 ,  G11C29/846

摘要： It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, square DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.

摘要翻译： 本发明的目的是提供一种半导体存储器件，其中即使对于较大数量的位也可有效地修复故障。 在能够在接收到地址时同时交换多个数据的多位存储器中，通常用于每个I / O的方形DQ线（15c），备用读出放大器电路（13c），备用列开关（14c） ，用于存储其中发生故障的DQ线的地址的保险丝盒（20）和用于存储故障DQ的I / O的熔丝电路（21-1,21-2 ...） 排列的行被排列以补救每个I / O的故障。 由于只有属于发生故障的一个I / O的存储单元被替换，所以不执行不必要的替换，并且即使对于较大数量的位也能够有效地补救存储单元。

公开(公告)号：US6084453A

公开(公告)日：2000-07-04

申请号：US105959

申请日：1998-06-29

申请人： Tsuneaki Fuse ,  Masahiro Kamoshida ,  Haruki Toda ,  Yukihito Oowaki

发明人： Tsuneaki Fuse ,  Masahiro Kamoshida ,  Haruki Toda ,  Yukihito Oowaki

IPC分类号： H03K5/04 ,  G06F1/06 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03K5/156 ,  H03K7/08

CPC分类号： H03K5/1565 ,  H03K5/133

摘要： A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.

摘要翻译： 周期测量电路3测量大约是单位时间的m倍的外部时钟信号的周期。 数字转换电路5和时间转换电路7协调，产生延迟了单位时间的m / 2K倍的脉冲信号，或者是外部时钟信号的周期的1 / 2K倍。 逻辑电路8产生与外部时钟信号同步上升的内部时钟信号，并且与延迟的脉冲信号同步地下降。 因此，内部时钟信号具有与外部时钟信号相同的周期，并且具有（1 / 2K）×100％的期望占空比。

公开(公告)号：US6034901A

公开(公告)日：2000-03-07

申请号：US327592

申请日：1999-06-08

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/407 ,  G06F1/10 ,  G06F13/42 ,  G11C7/22 ,  G11C19/00 ,  H03K5/135 ,  H03L7/00 ,  G11C7/00

CPC分类号： G11C7/225 ,  G11C7/22 ,  G11C7/222

摘要： An external clock signal CK is input to a buffer, which generates an internal clock signal CLK having a skew of D1 with respect to the external clock signal CK. The internal clock signal is input first to a delay circuit which has a delay time A, then to a delay array which provides a delay time D2, and finally to a delay circuit which has a delay time of D2. The delay circuit generates a corrected internal clock signal CK' which is synchronous with the external clock signal CK. The delay array is composed of delay units, each having a state-holding section. The state-holding section of any delay unit that has passed a forward pulse is set in a predetermined state. Once its state-holding section is set in the predetermined state, the delay unit provides a correct delay time of 2.times..DELTA..

摘要翻译： 外部时钟信号CK被输入到缓冲器，其产生相对于外部时钟信号CK具有D1偏斜的内部时钟信号CLK。 内部时钟信号首先输入到具有延迟时间A的延迟电路，然后输入到提供延迟时间D2的延迟阵列，最后输入延迟时间为D2的延迟电路。 延迟电路产生与外部时钟信号CK同步的经校正的内部时钟信号CK'。 延迟阵列由延迟单元组成，每个延迟单元具有状态保持部分。 已经通过正向脉冲的任何延迟单元的状态保持部分被设置在预定状态。 一旦其状态保持部分被设置在预定状态，则延迟单元提供2x DELTA的正确的延迟时间。

公开(公告)号：US5986968A

公开(公告)日：1999-11-16

申请号：US113570

申请日：1998-07-10

申请人： Haruki Toda ,  Hitoshi Kuyama

发明人： Haruki Toda ,  Hitoshi Kuyama

IPC分类号： G11C7/10 ,  G11C8/04 ,  G11C7/00

CPC分类号： G11C8/04 ,  G11C7/1045 ,  G11C7/1072

摘要： A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section for inputting a row enable control signal (/RE) and the column enable control signal (/CE) provided from an external device, other than the basic clock signal, for which the control signals are at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory cells, and a data I/O section for executing a data access operation for the address set by the control section. In the device, the output of data from the memory cells through the data I/O section is started after the setting of the initial address by the control sections and after a specified number of basic clock signals has been counted by the count section.

摘要翻译： 时钟同步半导体存储器件包括以矩阵形式布置的许多存储器单元，用于对连续的外部供给的基本时钟信号的实际循环次数进行计数的计数部分，用于输入行使能控制信号（/ RE）的控制部分， 以及与基本时钟信号不同的外部设备提供的与基本控制信号同步的指令级别的列使能控制信号（/ CE），并且用于设置用于数据访问的初始地址 以及用于执行由控制部分设置的地址的数据访问操作的数据I / O部分。 在设备中，通过控制部分设置初始地址之后，在计数部分计数了指定数量的基本时钟信号之后，通过数据I / O部分从存储器单元输出数据。

公开(公告)号：US5926436A

公开(公告)日：1999-07-20

申请号：US17948

申请日：1998-02-03

申请人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

发明人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04 ,  G11C11/407 ,  G11C11/41 ,  G11C11/413 ,  H01L27/10 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1018 ,  G11C7/22

摘要： A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.

摘要翻译： 半导体存储器件包括存储单元组，所述存储单元组包括排列成矩阵的多个存储器单元; 指定电路，用于依次指定存储器单元中由连续地址寻址的存储器单元，并将其输入激活状态; 用于对由指定电路指定的连续存储单元进行数据读出/写入操作（数据I / O操作）的数据输入/输出（I / O）电路，该控制基于读出/ 从外部部分提供的写入信号; 用于对从外部提供的基本时钟信号的周期数进行计数的计数器电路; 以及控制器，用于接收从外部部分提供的至少一个或多个指定信号，用于每个指定信号输出用于指定特定周期的控制信号作为开始周期，以对基本时钟信号的周期数进行计数，并且 指示计数器电路基于控制信号对基本时钟信号的计数数进行计数，并且用于控制由指定电路执行的指定操作和数据I / O电路的数据I / O操作，使得 控制存储单元组的存储器访问操作。

公开(公告)号：US5926431A

公开(公告)日：1999-07-20

申请号：US725542

申请日：1996-10-03

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/407 ,  G11C5/02 ,  G11C7/02 ,  G11C7/10 ,  G11C7/18 ,  G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C29/12 ,  G11C5/025 ,  G11C7/10 ,  G11C7/18

摘要： Banks are arranged on a memory chip, forming a matrix. A data input/output circuit is provided at one side of the memory chip. A data bus is provided among the banks and connected to the data input/output circuit. Each bank has a plurality of memory cell arrays a cell-array controller, a row decoder, column decoders, and a DQ buffer. The cell-array controller and the row decoder oppose each other. The column decoders oppose the DQ buffer. Local DQ lines are provided between the memory cell arrays, and global DQ liens extend over the memory cell arrays. The local DQ lines extend at right angles to the global DQ lines.

摘要翻译： 银行被布置在存储芯片上，形成矩阵。 数据输入/输出电路设置在存储芯片的一侧。 一个数据总线被提供在各个存储体之间并连接到数据输入/输出电路。 每个存储体具有多个存储单元阵列，单元阵列控制器，行解码器，列解码器和DQ缓冲器。 单元阵列控制器和行解码器彼此相对。 列解码器与DQ缓冲区相对。 在存储单元阵列之间提供局部DQ线，并且全局DQ留置线延伸到存储器单元阵列上。 局部DQ线与全局DQ线成直角延伸。

公开(公告)号：US5867432A

公开(公告)日：1999-02-02

申请号：US839037

申请日：1997-04-23

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/407 ,  G06F1/10 ,  G06F13/42 ,  G11C7/22 ,  G11C19/00 ,  H03K5/135 ,  H03L7/00 ,  G11C7/00

CPC分类号： G11C7/225 ,  G11C7/22 ,  G11C7/222

摘要： An external clock signal CK is input to a buffer, which generates an internal clock signal CLK having a skew of D1 with respect to the external clock signal CK. The internal clock signal is input first to a delay circuit which has a delay time A, then to a delay array which provides a delay time D2, and finally to a delay circuit which has a delay time of D2. The delay circuit generates a corrected internal clock signal CK' which is synchronous with the external clock signal CK. The delay array is composed of delay units, each having a state-holding section. The state-holding section of any delay unit that has passed a forward pulse is set in a predetermined state. Once its state-holding section is set in the predetermined state, the delay unit provides a correct delay time of 2.times..DELTA..

公开(公告)号：US5737637A

公开(公告)日：1998-04-07

申请号：US720309

申请日：1996-09-27

申请人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

发明人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04 ,  G11C11/407 ,  G11C11/41 ,  G11C11/413 ,  H01L27/10 ,  G06F13/00

CPC分类号： G11C7/1072 ,  G11C7/1018 ,  G11C7/22

摘要： A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for setting them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled,

摘要翻译： 半导体存储器件包括存储单元组，所述存储单元组包括排列成矩阵的多个存储器单元; 指定电路，用于根据存储单元中的连续地址指定顺序地存储单元，并将其设置为活动状态; 用于对由指定电路指定的连续存储单元进行数据读出/写入操作（数据I / O操作）的数据输入/输出（I / O）电路，该控制基于读出/ 从外部部分提供的写入信号; 用于对从外部提供的基本时钟信号的周期数进行计数的计数器电路; 以及控制器，用于接收从外部部分提供的至少一个或多个指定信号，用于每个指定信号输出用于指定特定周期的控制信号作为开始周期，以对基本时钟信号的周期数进行计数，并且 指示计数器电路基于控制信号对基本时钟信号的计数数进行计数，并且用于控制由指定电路执行的指定操作和数据I / O电路的数据I / O操作，使得 对存储单元组的存储器存取操作进行控制，

公开(公告)号：US5715211A

公开(公告)日：1998-02-03

申请号：US718786

申请日：1996-09-24

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C7/103 ,  G11C7/1072

摘要： A synchronous DRAM has cell arrays arranged in a matrix, divided into banks accessed asynchronously, and n bit I/O buses for transferring data among the cell arrays. In the DRAM, the banks are divided into m blocks, the n-bit I/O buses located between adjacent banks, are used for time sharing between adjacent banks in common, the n bit I/O buses, used for time sharing between adjacent banks in common, are grouped into n/m-bit I/O buses, every n/m bits for each block of m blocks of bank, and in each block in each bank, data input/output are carried out between the n/m-bit I/O buses and data bus lines in each block. A synchronous DRAM includes first and second internal clock systems for controlling a burst data transfer in which a string of burst data being transferred in synchronism with an external clock signal, when one of the internal clock systems is driven, the burst data transfer is commenced immediately by the selected internal clock system.

摘要翻译： 同步DRAM具有排列成矩阵的单元阵列，被划分为异步访问的存储体和用于在单元阵列之间传送数据的n位I / O总线。 在DRAM中，这些存储体分为m个块，位于相邻的存储体之间的n位I / O总线被用于相邻存储体之间的共享时间，n位I / O总线用于在相邻存储体之间进行时间共享 共同的组合被分组为n / m位I / O总线，每个m个块的每个块的每n / m位，并且在每个存储体的每个块中，数据输入/输出在n / 每个块中的m位I / O总线和数据总线。 同步DRAM包括用于控制突发数据传输的第一和第二内部时钟系统，其中当内部时钟系统中的一个被驱动时，脉冲串数据串与外部时钟信号同步传输，突发数据传输立即开始 由选定的内部时钟系统。