公开(公告)号：US09391544B2

公开(公告)日：2016-07-12

申请号：US12620929

申请日：2009-11-18

Applicant: Frederic Bonvin

Inventor： Frederic Bonvin

IPC: H02P6/14 ,  H02P3/14 ,  H02P3/22 ,  H02M7/5388 ,  H02P6/08 ,  H02P7/29 ,  H02P7/18 ,  G05F1/00

CPC classification number: H02P3/22 ,  G11B19/20 ,  H02M7/5388 ,  H02P6/085

Abstract: A drive circuit having asymmetrical drivers. In an embodiment, a brushless DC motor may be driven by a drive circuit having three high-side MOSFETs and three low-side MOSFETs. A driver controller turns the MOSFETs on and off according to a drive algorithm such that phase currents are injected into motor coils to be driven. The high-side MOSFETs may be sized differently than the low-side MOSFETs. As such, when a MacDonald waveform (or similar drive algorithm) is used to drive the phases of the motor, less power may be required during disk spin-up because the MOSFETs that are on more (e.g., the low-side MOSFETs with a MacDonald waveform) may be sized larger than the MOSFETs that are on less (e.g., the high-side MOSFETs). In this manner, less power is dissipated in the larger size MOSFETs that are on more than the others.

Abstract translation: 具有不对称驱动器的驱动电路。 在一个实施例中，无刷直流电动机可以由具有三个高边MOSFET和三个低边MOSFET的驱动电路驱动。 驱动器控制器根据驱动算法开启和关闭MOSFET，使得相电流被注入要驱动的电机线圈中。 高端MOSFET的尺寸可能与低端MOSFET的尺寸不同。 因此，当MacDonald波形（或类似的驱动算法）用于驱动电动机的相位时，由于更多的MOSFET（例如，具有一个或多个）的低端MOSFET，因此在磁盘启动期间可能需要更少的功率 麦克唐纳波形）的尺寸可能大于较少的MOSFET（例如高边MOSFET）。 以这种方式，在比其他MOSFET更大的MOSFET中消耗更少的功率。

公开(公告)号：US09391020B2

公开(公告)日：2016-07-12

申请号：US14314945

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen Spooner ,  Nicole A. Saulnier

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract translation: 公开了一种容纳小金属线和扩大直径通孔的波浪线互连结构。 扩大的直径通孔可以使用自对准双镶嵌工艺形成，而不需要单独的通孔光刻掩模。 扩大的直径通孔与下面的金属线的至少三侧直接接触，并且可以相对于金属线不对称地对准，以增加金属图案的堆积密度。 所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。 具有扩大的直径通孔的互连结构也可以具有气隙，以减少电介质击穿的机会。 通过允许通孔占地面积超过金属线宽度的最小尺寸，可以为进一步的工艺世代清除路径，以继续将金属线收缩到低于10nm的尺寸。

公开(公告)号：US09390967B2

公开(公告)日：2016-07-12

申请号：US14567567

申请日：2014-12-11

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Joe Lee ,  Yann Mignot ,  Brown C. Peethala

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76843

Abstract: A selective wet etching process is used, prior to air gap opening formation, to remove a sacrificial nitride layer from over a first region of an interconnect dielectric material containing a plurality of first conductive metal structures utilizing a titanium nitride hard mask portion located over a second region of the interconnect dielectric material as an etch mask. The titanium nitride hard mask portion located over the second region of the interconnect dielectric material is thereafter removed, again prior to air gap opening formation, utilizing another wet etch process. The wet etching processes are used instead of reactive ion etching.

Abstract translation: 在气隙开口形成之前使用选择性湿法蚀刻工艺，以从包含多个第一导电金属结构的互连电介质材料的第一区域上方移除牺牲氮化物层，所述第一导电金属结构利用位于第二层上的氮化钛硬掩模部分 互连电介质材料的区域作为蚀刻掩模。 此后，在气隙开口形成之前，再次移除位于互连电介质材料的第二区域之上的氮化钛硬掩模部分，利用另一湿蚀刻工艺。 使用湿蚀刻工艺代替反应离子蚀刻。

公开(公告)号：US09385051B2

公开(公告)日：2016-07-05

申请号：US14822959

申请日：2015-08-11

Applicant: STMicroelectronics, Inc.

Inventor： Ronald K. Sampson ,  Nicolas Loubet

IPC: H01L21/84 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract translation: 将半导体材料图案化以限定与底层基板绝缘的细长翅片。 多晶硅半导体材料沉积在细长翅片之上并在细长翅片之间，并且被图案化以限定延伸到在晶体管沟槽处垂直交叉在细长翅片上的细长门。 侧壁间隔件形成在细长门的侧壁上。 位于细长门之间的细长翅片的部分与下面的绝缘体一起被去除以暴露下面的基底。 然后在细长门之间的位置从下面的衬底外延生长一个或多个半导体材料层。 一个或多个半导体材料层可以包括未掺杂的外延层和上覆的掺杂外延层。 外延材料限定晶体管的源极或漏极。

公开(公告)号：US20160149037A1

公开(公告)日：2016-05-26

申请号：US14950833

申请日：2015-11-24

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMICROELECTRONICS, Inc.

Inventor： Shay REBOH ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: Method of making at least one transistor strained channel semiconducting structure, comprising steps to form a sacrificial gate block and insulating spacers arranged in contact with the lateral faces of the sacrificial gate block, form sacrificial regions in contact with the lateral faces of said semiconducting zone, said sacrificial regions being configured so as to apply a strain on said semiconducting zone, remove said sacrificial gate block between said insulating spacers, replace said sacrificial gate block by a replacement gate block between said insulating spacers, remove said sacrificial regions, and replace said sacrificial regions by replacement regions in contact with the lateral faces of said semiconducting zone, on a semiconducting zone that will form a transistor channel region.

Abstract translation: 制造至少一个晶体管应变通道半导体结构的方法，包括形成牺牲栅极块的步骤和与牺牲栅极块的侧面接触地布置的绝缘间隔物，形成与所述半导体区域的侧面接触的牺牲区域， 所述牺牲区域被配置为在所述半导体区域上施加应变，去除所述绝缘间隔物之间​​的所述牺牲栅极块，用所述绝缘间隔物之间​​的置换栅极块代替所述牺牲栅极块，去除所述牺牲区域， 区域，其与形成晶体管沟道区域的半导体区域相接触，与所述半导体区域的侧面接触。

公开(公告)号：US20160133736A1

公开(公告)日：2016-05-12

申请号：US14945936

申请日：2015-11-19

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  John Hongguang Zhang

IPC: H01L29/772 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7722 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/308 ,  H01L27/0225 ,  H01L27/14679 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66416

Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.

Abstract translation: 在掺杂有第一导电类型的碳化硅衬底上形成静电感应晶体管。 在碳化硅衬底的顶表面中的第一凹陷区域填充有原位掺杂有第二导电类型的外延生长栅极区域。 原位掺杂有第一导电类型的外延生长沟道区位于相邻的外延栅区之间。 原位掺杂有第一导电类型的外延生长的源极区位于外延沟道区上。 碳化硅衬底的底表面包括与沟道区垂直对准的第二凹陷区域并硅​​化以支持漏极接触的形成。 源区的顶表面被硅化以支持源接触的形成。 栅极引线外延生长并电耦合到栅极区域，栅极引线硅化以支持栅极接触的形成。

公开(公告)号：US09326234B2

公开(公告)日：2016-04-26

申请号：US13710282

申请日：2012-12-10

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W52/02 ,  H04W52/14

CPC classification number: H04W52/0206 ,  H04W52/0219 ,  Y02D70/142

Abstract: Methods and systems are disclosed for reduced power consumption in communication networks, including sensor networks implemented according to IEEE 802.11ah, by organizing stations into groups having long sleep periods. By organizing the stations of the network into groups, the access point can match each group's traffic identification map with its target beacon transmit time. One embodiment organizes the stations sequentially by AID numbers. Other embodiments organize the stations by similar power save requirements and/or nearby geographical location. Forms of an Extended Traffic Identification Map are matched with an awaken Target Beacon Transmit Time of the group.

Abstract translation: 公开的方法和系统通过将站组织成具有长睡眠周期的群组来降低通信网络中的功耗，包括根据IEEE 802.11ah实现的传感器网络。 通过将网络组合成组，接入点可以将每个组的流量识别图与其目标信标发送时间相匹配。 一个实施例按照AID号顺序组织站。 其他实施例通过类似的省电要求和/或附近的地理位置组织站。 扩展流量识别图的形式与组的唤醒目标信标发送时间相匹配。

公开(公告)号：US09324370B2

公开(公告)日：2016-04-26

申请号：US12860653

申请日：2010-08-20

Applicant: Shayan Srinivasa Garani ,  Sivagnanam Parthasarathy

Inventor： Shayan Srinivasa Garani ,  Sivagnanam Parthasarathy

IPC: G11B27/36 ,  G11B20/18 ,  G11B20/10

CPC classification number: G11B20/1833 ,  G06F11/2094 ,  G06F2201/805 ,  G06F2201/85 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/10222 ,  G11B20/10287 ,  G11B20/10296 ,  G11B20/10379 ,  G11B2020/1823 ,  G11B2020/1826 ,  G11B2020/185 ,  G11B2020/1863 ,  G11B2220/2516

Abstract: An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region.

Abstract translation: 数据读取路径的实施例包括缺陷检测器和数据恢复电路。 缺陷检测器可操作以识别数据存储介质的缺陷区域，并且数据恢复电路可操作以响应于缺陷检测器从数据存储介质中恢复数据。 例如，这样的实施例可以允许识别例如由划痕或污染导致的数据存储盘的缺陷区域，并且可以允许恢复写入到缺陷区域的数据。

公开(公告)号：US20160112598A1

公开(公告)日：2016-04-21

申请号：US14982335

申请日：2015-12-29

Applicant: STMicroelectronics, Inc.

Inventor： Francis C. STAFFORD

IPC: H04N1/195 ,  H04N1/60 ,  H04N1/10

CPC classification number: H04N1/19594 ,  H04N1/00827 ,  H04N1/10 ,  H04N1/46 ,  H04N1/60 ,  H04N2201/0081 ,  H04N2201/0084

Abstract: A method and apparatus for acquiring a corrected digital image of an object includes a digital camera operable to capture a plurality of color component images, an imager body and a support arm. The support arm is coupled to the imager body and adapted to support the digital camera. An image processor is provided to produce corrected color component images and an image combiner is provided to combine the corrected color component images to form the corrected digital image. The camera is moveable to more than one position to enable to formation of three-dimensional images or images with increased depth of focus.

Abstract translation: 用于获取对象的校正数字图像的方法和装置包括可操作以捕获多个颜色分量图像的数字照相机，成像器主体和支撑臂。 支撑臂联接到成像器主体并且适于支撑数字照相机。 提供图像处理器以产生校正的颜色分量图像，并且提供图像组合器以组合校正的颜色分量图像以形成校正的数字图像。 相机可以移动到多于一个位置，以使得能够形成具有增加的焦深的三维图像或图像。

公开(公告)号：US09299721B2

公开(公告)日：2016-03-29

申请号：US14280998

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L21/30 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Abstract translation: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物，以及在第二半导体区域上方并邻近间隔物形成第三半导体区域，其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分，从第一半导体区域形成第一组散热片，以及从第二和第三半导体区域形成第二组散热片。