公开(公告)号：US10483377B2

公开(公告)日：2019-11-19

申请号：US15821091

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L29/66 ,  H01L29/78

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

公开(公告)号：US10483154B1

公开(公告)日：2019-11-19

申请号：US16015351

申请日：2018-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Marcus Wolf ,  Carsten Peters ,  Markus Lenski ,  Loic Gaben

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06

Abstract: In various aspects, the present disclosure relates to device structures and a method of forming such a device structure. In some illustrative embodiments herein, a device is provided, including a semiconductor substrate having a first trench formed therein, and a first trench isolation structure formed in the first trench. The first trench isolation structure includes first and second insulating liners formed adjacent inner surfaces of the first trench, wherein the first insulating liner is in direct contact with inner surfaces of the first trench and the second insulating liner is formed directly on the first insulating liner, and a first insulating filling material which at least partially fills the first trench. In some aspects, a thickness of the first insulating liner is greater than a thickness of the second insulating liner.

公开(公告)号：US10475921B2

公开(公告)日：2019-11-12

申请号：US15888195

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: An LDFET may be formed on the basis of manufacturing platforms designed for forming sophisticated small signal transistor elements. To this end, sidewall areas of trench isolation regions laterally positioned within the drift region may be used as current paths, thereby achieving increased design flexibility, since efficient current paths may still be established, even if the trench isolation regions have to extend into the substrate material due to design criteria determined by the sophisticated small signal transistor elements. In some illustrative embodiments, isolation of P-LDFETs with respect to the P-substrate may be accomplished without requiring a deep well implantation.

公开(公告)号：US10475899B2

公开(公告)日：2019-11-12

申请号：US16190549

申请日：2018-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786 ,  H01L27/088

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

公开(公告)号：US10468456B2

公开(公告)日：2019-11-05

申请号：US15898562

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.

公开(公告)号：US10468310B2

公开(公告)日：2019-11-05

申请号：US15334964

申请日：2016-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei Peng ,  Xusheng Wu

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.

公开(公告)号：US10468083B1

公开(公告)日：2019-11-05

申请号：US16010841

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C5/06 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01L43/12 ,  H01L43/10

Abstract: Integrated circuits and methods of operating and producing the same are provided. In an exemplary embodiment, an integrated circuit includes a look up table with a first and second memory cell. The first memory cell includes a first magneto electric (ME) layer, a first free layer adjacent to the first ME layer, and a first fixed layer. The second memory cell includes a second ME layer, a second free layer adjacent to the second ME layer, and a second fixed layer. A first word line is in direct communication with the first and second free layers, wherein direct communication is a connection through zero, one, or more intervening components that are electrical conductors. A first bit line is in direct communication with the first ME layer, and a second bit line is in direct communication with the second ME layer.

公开(公告)号：US10466514B1

公开(公告)日：2019-11-05

申请号：US16181879

申请日：2018-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02F1/035 ,  G02F1/225 ,  G02B6/122 ,  G02B6/136 ,  F21V8/00 ,  G02F1/015 ,  G02F1/21 ,  G02B6/12

Abstract: Structures for an electro-optic modulator and methods of fabricating such structures. A first plurality of cavities are formed in a bulk semiconductor substrate. A passive waveguide arm includes a first core arranged over the first plurality of cavities. The passive waveguide arm has an input port and an output port that is spaced lengthwise from the input port. An epitaxial semiconductor layer is arranged over the bulk semiconductor substrate, and includes a second plurality of cavities. An active waveguide arm includes a second core that is arranged over the second plurality of cavities. The second core of the active waveguide arm is coupled with the input port of the first core of the passive waveguide arm, and the second core of the active waveguide arm is also coupled with the output port of the first core of the passive waveguide arm.

公开(公告)号：US10461173B1

公开(公告)日：2019-10-29

申请号：US15990186

申请日：2018-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Xuan Anh Tran ,  Hui Zang ,  Bala Haran ,  Suryanarayana Kalaga

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.

公开(公告)号：US10461029B2

公开(公告)日：2019-10-29

申请号：US15686230

申请日：2017-08-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu Wong ,  Jagar Singh

IPC: H01L23/525 ,  H01L23/528 ,  H01L21/762 ,  H01L29/161

Abstract: Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed. In various embodiments, the e-fuse structure includes: a substrate; an insulator layer over the substrate; a pair of contact regions overlying the insulator layer; and a silicide channel overlying the insulator layer and connecting the pair of contact regions, the silicide channel having a first portion including silicide silicon and a second portion coupled with the first portion and on a common level with the first portion, the second portion including silicide silicon germanium (SiGe) or silicide silicon phosphorous (SiP).