公开(公告)号：US11979158B2

公开(公告)日：2024-05-07

申请号：US17825704

申请日：2022-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Yu Lin ,  Yung-Chen Chien ,  Jia-Hong Gao ,  Jerry Chang Jui Kao ,  Hui-Zhong Zhuang

IPC: H03K3/00 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104

Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

公开(公告)号：US11967596B2

公开(公告)日：2024-04-23

申请号：US17395126

申请日：2021-08-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guo-Huei Wu ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien ,  Lee-Chung Lu

IPC: H01L27/118 ,  G06F30/31 ,  G06F30/392 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/02 ,  H03K17/687

CPC classification number: H01L27/11807 ,  G06F30/31 ,  G06F30/392 ,  H01L21/76885 ,  H01L21/823871 ,  H01L27/0207 ,  H01L2027/11812 ,  H01L2027/11848 ,  H01L2027/11862 ,  H01L2027/11866 ,  H01L2027/11879 ,  H01L2027/11881 ,  H01L2027/11885 ,  H01L2027/11887 ,  H03K17/6872 ,  H03K17/6874

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

公开(公告)号：US20240105726A1

公开(公告)日：2024-03-28

申请号：US18517938

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Lun Chien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue

IPC: H01L27/092 ,  H01L21/765 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/765 ,  H01L21/823412 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922

Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

公开(公告)号：US11935888B2

公开(公告)日：2024-03-19

申请号：US16837497

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pin-Dai Sue ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Ya-Chi Chou ,  Chi-Yu Lu

IPC: H01L27/118 ,  G06F30/367 ,  G06F30/392 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/088 ,  G06F119/06

CPC classification number: H01L27/0886 ,  G06F30/367 ,  G06F30/392 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  G06F2119/06

Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.

公开(公告)号：US11907633B2

公开(公告)日：2024-02-20

申请号：US17818417

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Cheok-Kei Lei ,  Yu-Chi Li ,  Chia-Wei Tseng ,  Zhe-Wei Jiang ,  Chi-Lin Liu ,  Jerry Chang-Jui Kao ,  Jung-Chan Yang ,  Chi-Yu Lu ,  Hui-Zhong Zhuang

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.

公开(公告)号：US11855070B2

公开(公告)日：2023-12-26

申请号：US17390108

申请日：2021-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Hsin Tsai ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L27/02 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/092

Abstract: A semiconductor device, includes a first metal layer, a second metal layer, and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The at least one conductive via connects the first conductor and the second conductor through the third conductor.

公开(公告)号：US11842131B2

公开(公告)日：2023-12-12

申请号：US17222057

申请日：2021-04-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Mao-Wei Chiu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Chi-Yu Lu

IPC: G06F30/30 ,  G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F115/08 ,  H01L23/528 ,  H01L27/02

CPC classification number: G06F30/30 ,  G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F2115/08 ,  H01L23/528 ,  H01L27/0207

Abstract: A method for manufacturing a semiconductor device to which corresponds a layout diagram stored on a non-transitory computer-readable medium. The method includes generating the layout diagram using an electronic design system (EDS), the EDS including at least one processor and at least one memory including computer program code for one or more programs are configured to cause the EDS to execute the generating. Testing the semiconductor device. Revising, the layout diagram, based on testing results indicative of selected standard functional cells in the layout diagram which merit modification or replacement. Programming one or more of the ECO cells which correspond to the one or more selected standard functional cells resulting in one or more programmed ECO cells. Routing the one or more programmed ECO cells correspondingly to at least one of the selected standard functional cells or to one or more other ones of the standard functional cells.

公开(公告)号：US20230387015A1

公开(公告)日：2023-11-30

申请号：US18448005

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chun Tien ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Shun Li Chen ,  Ting Yu Chen

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L27/0924 ,  H01L21/823871 ,  H01L21/823821 ,  H01L23/5226

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

公开(公告)号：US11775727B2

公开(公告)日：2023-10-03

申请号：US16299973

申请日：2019-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Chin-Chou Liu ,  Hui-Zhong Zhuang ,  Meng-Kai Hsu ,  Pin-Dai Sue ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Chi-Yu Lu ,  Jung-Chou Tsai

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F119/18

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

公开(公告)号：US11764213B2

公开(公告)日：2023-09-19

申请号：US17214194

申请日：2021-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Yu Lai ,  Chih-Liang Chen ,  Chi-Yu Lu ,  Shang-Syuan Ciou ,  Hui-Zhong Zhuang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC: H01L27/06 ,  G06F30/394 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/66 ,  G06F30/392 ,  H01L23/48

CPC classification number: H01L27/0694 ,  G06F30/392 ,  G06F30/394 ,  H01L21/0259 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5283 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate and a first active region on a first side of the substrate. The semiconductor device further includes a first gate structure surrounding a first portion of the first active region. The semiconductor device further includes a second active region on a second side of the substrate, wherein the second side is opposite the first side. The semiconductor device further includes a second gate structure surrounding a first portion of the second active region. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.