公开(公告)号：US11716862B2

公开(公告)日：2023-08-01

申请号：US17116024

申请日：2020-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H Chiang ,  Chung-Te Lin

IPC: H01L27/12 ,  H10B99/00 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L27/124 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/7869

Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

公开(公告)号：US11706928B2

公开(公告)日：2023-07-18

申请号：US17166078

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L51/30 ,  H01L29/78 ,  H10B51/30 ,  H01L29/66

CPC classification number: H10B51/30 ,  H01L29/6684 ,  H01L29/78391

Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. This ferroelectric material may be of the composition HFxZr1-xO2. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). A ferroelectric layer formed with chlorine-free precursors has no chlorine residue. The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

公开(公告)号：US11683988B2

公开(公告)日：2023-06-20

申请号：US17221674

申请日：2021-04-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Sheng-Chih Lai ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H10N50/01 ,  H10B61/00 ,  G11C11/16 ,  H10N50/10 ,  H10N50/80 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/226 ,  H01L43/02 ,  H01L43/08

Abstract: A device includes a conductive feature, a dielectric layer, a bottom electrode via, and a liner layer. The dielectric layer is over the conductive feature. The bottom electrode via is in the dielectric layer and over the conductive feature. A topmost surface of the bottom electrode via is substantially flat. A liner layer cups an underside of the bottom electrode via. The liner layer has a topmost end substantially level with the topmost surface of the bottom electrode via.

公开(公告)号：US11652041B2

公开(公告)日：2023-05-16

申请号：US17378357

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Pin-Dai Sue

IPC: H01L23/522 ,  H01L27/118 ,  H01L27/02

CPC classification number: H01L23/5222 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US11637098B2

公开(公告)日：2023-04-25

申请号：US17315900

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Lee-Chung Lu ,  Po-Hsiang Huang ,  Chun-Chen Chen ,  Chung-Te Lin ,  Ting-Wei Chiang ,  Sheng-Hsiung Chen ,  Jung-Chan Yang

IPC: H01L27/00 ,  H01L27/02 ,  H01L27/118 ,  G06F30/394 ,  G06F30/392

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US20230057672A1

公开(公告)日：2023-02-23

申请号：US17981274

申请日：2022-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Chun-Chen Chen ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Chung-Te Lin ,  Jerry Chang Jul Kao ,  Sheng-Hsiung Chen ,  Chin-Chou Liu

IPC: H01L27/118 ,  G06F30/398 ,  H01L27/02

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

公开(公告)号：US11588107B2

公开(公告)日：2023-02-21

申请号：US17369671

申请日：2021-07-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L27/24 ,  H01L45/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.

公开(公告)号：US11587823B2

公开(公告)日：2023-02-21

申请号：US16951595

申请日：2020-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: G11C7/18 ,  H01L27/11597 ,  H01L21/8239 ,  H01L21/762

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

公开(公告)号：US20220285519A1

公开(公告)日：2022-09-08

申请号：US17319461

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.

公开(公告)号：US11195913B2

公开(公告)日：2021-12-07

申请号：US16826913

申请日：2020-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Gerben Doornbos ,  Chung-Te Lin

IPC: H01L21/82 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/40 ,  H01L29/08 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/02

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin structure over a substrate, and the fin structure includes alternately stacked semiconductor material layers and sacrificial layers. The method further includes forming a dummy gate structure, recessing the fin structure to form an opening, forming first source/drain spacers on sidewalls of the sacrificial layers by performing a first atomic layer deposition (ALD) process, and forming source/drain structure in the opening. The method further includes removing the dummy gate structure and the sacrificial layers to expose the semiconductor material layers and forming a gate structure wrapping around the semiconductor material layers.