公开(公告)号：US20240387253A1

公开(公告)日：2024-11-21

申请号：US18787268

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Jen Hung Wang ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.

公开(公告)号：US20240379346A1

公开(公告)日：2024-11-14

申请号：US18783614

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

公开(公告)号：US12142651B2

公开(公告)日：2024-11-12

申请号：US18166379

申请日：2023-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tze-Liang Lee

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. An etch stop layer is deposited over the dielectric cap. An interlayer dielectric (ILD) layer is deposited over the etch stop layer. The ILD layer is in contact with a sidewall of the etch stop layer. A gate via in the ILD layer is formed to pass through the etch stop layer and the dielectric cap to the gate structure.

公开(公告)号：US20240332068A1

公开(公告)日：2024-10-03

申请号：US18738256

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC: H01L21/768 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20 ,  H01L21/027

CPC classification number: H01L21/76823 ,  G03F7/038 ,  G03F7/039 ,  G03F7/2004 ,  G03F7/2022 ,  H01L21/0274 ,  H01L21/76802 ,  H01L21/76877

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US12074058B2

公开(公告)日：2024-08-27

申请号：US18308937

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76879

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

公开(公告)号：US12046475B2

公开(公告)日：2024-07-23

申请号：US17191105

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Tze-Liang Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/28247 ,  H01L21/76802 ,  H01L21/76816 ,  H01L29/401 ,  H01L29/66454 ,  H01L29/66795 ,  H01L21/31116 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/0886 ,  H01L29/41791

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

公开(公告)号：US12033890B2

公开(公告)日：2024-07-09

申请号：US18309131

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC: H01L21/768 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20 ,  H01L21/027

CPC classification number: H01L21/76823 ,  G03F7/038 ,  G03F7/039 ,  G03F7/2004 ,  G03F7/2022 ,  H01L21/0274 ,  H01L21/76802 ,  H01L21/76877

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US12002865B2

公开(公告)日：2024-06-04

申请号：US17326848

申请日：2021-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Liang Lee

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes depositing a dielectric layer, depositing a plurality of mandrel strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups. Each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups. The method further includes forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer and to form trenches in the dielectric layer, and filling a conductive material into the trenches to form a plurality of conductive features.

公开(公告)号：US11887851B2

公开(公告)日：2024-01-30

申请号：US17388209

申请日：2021-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Chang ,  Jei Ming Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877

Abstract: A method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. The mask layer is patterned using the patterned photoresist layer as a mask. A target layer is patterned using the patterned mask layer as a mask.

公开(公告)号：US20230387231A1

公开(公告)日：2023-11-30

申请号：US18366352

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Liang Lee

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/42376 ,  H01L29/785 ,  H01L29/66795 ,  H01L29/401 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4236 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475

Abstract: A method includes depositing a dielectric layer, depositing a plurality of mandrel strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups. Each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups. The method further includes forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer and to form trenches in the dielectric layer, and filling a conductive material into the trenches to form a plurality of conductive features.