公开(公告)号：US20140091881A1

公开(公告)日：2014-04-03

申请号：US14030357

申请日：2013-09-18

Applicant: STMicroelectronics SA

Inventor： Jean-Christophe Ricard ,  Cedric Durand ,  Frederic Gianesello

IPC: H03H7/01

CPC classification number: H03H7/0138 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/0161 ,  H03H7/075 ,  H03H7/12 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1783 ,  H03H7/1791 ,  H03H7/463

Abstract: A passive filter may include at least one elliptical filter unit and at least one asymmetric rejection filter unit coupled in series with the elliptical filter unit. The at least one asymmetric rejection filter unit may have a frequency response curve that includes a dip with different attenuations on either side, and an overshoot upon exiting the dip at the side with the lower attenuation.

Abstract translation: 无源滤波器可以包括至少一个椭圆滤波器单元和与椭圆滤波器单元串联耦合的至少一个不对称拒绝滤波器单元。 所述至少一个不对称拒绝滤波器单元可以具有频率响应曲线，其包括在任一侧具有不同衰减的倾角，以及在具有较低衰减的一侧退出倾斜时的过冲。

公开(公告)号：US20140091846A1

公开(公告)日：2014-04-03

申请号：US14040781

申请日：2013-09-30

Applicant: STMicroelectronics SA

Inventor： Francois Agut

IPC: H03K3/3565

CPC classification number: H03K3/3565 ,  H03K3/02337

Abstract: A comparator circuit includes an input differential amplifier circuit generating an output signal and an inverting output circuit generating a complemented output signal. The differential amplifier circuit is formed of a differential pair of input transistors and a pair of diode connected load transistors. The comparator circuit is integrated in a silicon on insulator type structure. A hysteresis-creating circuit is formed by coupling one or more of the output signal and complemented output signal to a substrate region (in the silicon on insulator type structure) associated with one or more of the differential pair of input transistors and pair of diode connected load transistors. The differential amplifier circuit may further include auxiliary transistors coupled to the diode connected load transistors and the hysteresis-creating circuit may further couple one or more of the output signal and complemented output signal to the substrate region associated with the auxiliary transistor.

Abstract translation: 比较器电路包括产生输出信号的输入差分放大器电路和产生补码输出信号的反相输出电路。 差分放大器电路由差分输入晶体管和一对二极管连接的负载晶体管组成。 比较器电路集成在绝缘体上的绝缘体结构中。 通过将输出信号和补充输出信号中的一个或多个耦合到与一个或多个差分输入晶体管和二极管连接的一个或多个的衬底区域（在绝缘体上的绝缘体结构中）形成磁滞产生电路 负载晶体管。 差分放大器电路还可以包括耦合到二极管连接的负载晶体管的辅助晶体管，并且产生滞后的电路还可将输出信号和补码输出信号中的一个或多个耦合到与辅助晶体管相关联的衬底区域。

公开(公告)号：US20040252571A1

公开(公告)日：2004-12-16

申请号：US10894286

申请日：2004-07-19

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Francois Hugues ,  Philippe Roche

IPC: G11C005/00

CPC classification number: H03K19/00338 ,  H03K19/0075

Abstract: A circuit (200) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN1, CN2, CP1, CP2) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.

Abstract translation: 用于防止电压或电流尖峰的电路（200）接收初始时钟信号（CI），并将至少一个合成时钟信号（CN1，CN2，CP1，CP2）发送到下游电路。 如果随机电压或电流尖峰出现在上游，则该合成时钟信号无效。 这避免了干扰下游电路的操作的可能性。 应用于集成电路的时钟电路保护。

公开(公告)号：US20040187088A1

公开(公告)日：2004-09-23

申请号：US10770836

申请日：2004-02-03

Applicant: STMicroelectronics SA

Inventor： Joel Cambonie

IPC: G06F017/50

CPC classification number: H03K19/17736 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/1774 ,  Y02D10/12 ,  Y02D10/13

Abstract: The configurable electronic device comprises a configurable electronic device includes at least one configurable basic assembly. The basic assembly includes a programmable circuit having a plurality of programmable elements, and a first configurable interconnection network for mutually connecting the programmable circuits. A plurality of configurable arithmetic cells are mutually connected by a second configurable interconnection network. A third configurable interconnection network links the programmable circuit and the configurable arithmetic cells. A control bus is between the programmable circuit and the configurable arithmetic cells, and also extends within the configurable arithmetic cells.

Abstract translation: 可配置电子设备包括可配置电子设备，其包括至少一个可配置的基本组件。 基本组件包括具有多个可编程元件的可编程电路和用于相互连接可编程电路的第一可配置互连网络。 多个可配置的算术单元通过第二可配置互连网络相互连接。 第三可配置互连网络链接可编程电路和可配置的算术单元。 控制总线在可编程电路和可配置的算术单元之间，并且还可在可配置的算术单元内延伸。

公开(公告)号：US20030216088A1

公开(公告)日：2003-11-20

申请号：US10436881

申请日：2003-05-13

Applicant: STMicroelectronics SA

Inventor： Olivier Tardieu ,  Christophe Moreaux ,  Ahmed Kari

IPC: H01R009/22

CPC classification number: H03K19/09429

Abstract: A buffer of reduced size includes a logic gate to raise the potential level of input digital data having a first logic level to a potential equal to a low power supply potential, and to produce intermediate data if a validation signal is active. The buffer also includes a tristate inverter to produce output data, at an output, that are logically inverse to the intermediate data if the validation signal is active and having its output at high impedance if otherwise. Such a buffer is particularly useful as an output buffer for contact cards using a power supply potential different from a potential powering a reader with which the card communicates.

Abstract translation: 减小尺寸的缓冲器包括逻辑门，以将具有第一逻辑电平的输入数字数据的电位电平提高到等于低电源电位的电位，并且如果有效信号是有效的，则产生中间数据。 缓冲器还包括一个三态反相器，用于在输出端产生与中间数据逻辑相反的输出数据，如果验证信号是有效的，并且如果有的话，其输出为高阻抗。 这样的缓冲器特别适用于使用电源电位不同于为卡通信的读取器供电的接触卡的输出缓冲器。

公开(公告)号：US20030214772A1

公开(公告)日：2003-11-20

申请号：US10191089

申请日：2002-07-09

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Francois Hugues ,  Philippe Roche ,  Richard Ferrant

IPC: H01H073/00

CPC classification number: H03K19/00338 ,  H03K19/0075

Abstract: A circuit (200) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN1, CN2, CP1, CP2) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.

Abstract translation: 用于防止电压或电流尖峰的电路（200）接收初始时钟信号（CI），并将至少一个合成时钟信号（CN1，CN2，CP1，CP2）发送到下游电路。 如果随机电压或电流尖峰出现在上游，则该合成时钟信号无效。 这避免了干扰下游电路的操作的可能性。 应用于集成电路的时钟电路保护。

公开(公告)号：US20030186658A1

公开(公告)日：2003-10-02

申请号：US10360833

申请日：2003-02-07

Applicant: STMicroelectronics SA

Inventor： Jean Ravatin ,  Michel Mouret ,  Francois Van Zanten

IPC: H04B001/00

CPC classification number: H04B1/30

Abstract: The method includes an adjustment phase in which a filtering device is operated as an oscillator, the frequency of oscillation of the filtering device is determined, and the characteristics of the filtering device are corrected with respect to the determined oscillation frequency and to a pre-established relation between the frequency of oscillation and the theoretical cutoff frequency, in such a way as to confer upon the filtering device a cutoff frequency equal to the theoretical cutoff frequency to within a tolerance. After the adjustment phase, a working phase takes place in which the filtering device carries out its filtering function.

Abstract translation: 该方法包括滤波装置作为振荡器操作的调整相位，确定滤波装置的振荡频率，并且根据确定的振荡频率校正滤波装置的特性，并将其预先建立 振荡频率与理论截止频率之间的关系，以使得滤波装置将等于理论截止频率的截止频率提供到容限内。 在调整阶段之后，进行过滤装置进行过滤功能的工作阶段。

公开(公告)号：US20030016563A1

公开(公告)日：2003-01-23

申请号：US10178081

申请日：2002-06-21

Applicant: STMicroelectronics SA

Inventor： Christophe Frey

IPC: G11C005/00

CPC classification number: G11C11/41

Abstract: A memory cell is formed with a buffer circuit. The output of the buffer circuit is linked to the input to form a logic latch. A write-access transistor is disposed between a first node linked to a bit line and the input of the buffer circuit. A control gate of the write-access transistor is linked to a second node linked to a write word line, and a read-access transistor is disposed between a first node linked to a bit line and a second node linked to a read word line. A control gate of the read-access transistor is linked to the output of the buffer circuit.

Abstract translation: 存储单元形成有缓冲电路。 缓冲电路的输出端与输入端相连，构成逻辑锁存器。 写访问晶体管设置在链接到位线的第一节点和缓冲电路的输入之间。 写访问晶体管的控制栅极链接到链接到写字线的第二节点，并且读访问晶体管设置在链接到位线的第一节点和链接到读字线的第二节点之间。 读取存取晶体管的控制栅极连接到缓冲电路的输出端。

公开(公告)号：US11996465B2

公开(公告)日：2024-05-28

申请号：US17486000

申请日：2021-09-27

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/06 ,  H01L29/73

CPC classification number: H01L29/66234 ,  H01L21/22 ,  H01L29/0649 ,  H01L29/73

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

公开(公告)号：US11978530B2

公开(公告)日：2024-05-07

申请号：US17556039

申请日：2021-12-20

Applicant: STMicroelectronics SA

Inventor： Faress Tissafi Drissi

IPC: G11C7/24 ,  G11C11/419

CPC classification number: G11C7/24 ,  G11C11/419

Abstract: A memory includes memory cells arranged in rows and in columns, with at least one bit line for each column being coupled to the memory cells of the column. A read/write circuit is coupled to the bit lines and is configured to receive, for each column, a binary datum to be stored in one of the memory cells of the column. The read/write circuit includes, for each column, a latch configured to store a bit of a key, and an encryption circuit configured to encrypt the received binary datum with the bit of the key to provide encrypted binary datum. The read/write circuit controls the bit line to thereby store the encrypted binary datum.