公开(公告)号：US20170092678A1

公开(公告)日：2017-03-30

申请号：US15280544

申请日：2016-09-29

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Romain Girard Desprolet ,  Michel Marty ,  Salim Boutami ,  Sandrine Lhostis

IPC: H01L27/146 ,  G02B5/20 ,  H01L21/311

CPC classification number: H01L27/14625 ,  B82Y20/00 ,  G02B5/008 ,  G02B5/201 ,  G02B5/204 ,  G02B2207/101 ,  G02F1/133509 ,  G02F1/133516 ,  H01L21/311 ,  H01L27/14621 ,  H01L27/14685

Abstract: A spectral filter is manufactured using a process wherein a first rectangular bar is formed within a first layer made of a first material, said first rectangular bar being made of a second material having a different optical index. The process further includes, in a second layer over the first layer, a second rectangular bar made of the second material. The second rectangular bar is positioned in contact with the first rectangular bar. The second layer is also made of the first material.

公开(公告)号：US09590127B2

公开(公告)日：2017-03-07

申请号：US14335095

申请日：2014-07-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/00 ,  H01L31/103 ,  H01L27/146 ,  H04N5/378

CPC classification number: H01L31/103 ,  H01L27/14612 ,  H01L27/14643 ,  H04N5/378

Abstract: An image sensor cell formed inside and on top of a substrate of a first conductivity type, including: a read region of the second conductivity type; and, adjacent to the read region, a storage region of the first conductivity type topped with a first insulated gate electrode. The first electrode is arranged to receive, in a first operating mode, a first voltage causing the inversion of the conductivity type of the storage region, so that the storage region behaves as an extension of the read region, and, in a second operating mode, a second voltage causing no inversion of the storage region.

Abstract translation: 在第一导电类型的衬底的内部和顶部形成的图像传感器单元，包括：第二导电类型的读取区域; 并且与读取区域相邻的第一导电类型的存储区域顶上第一绝缘栅电极。 第一电极被布置成在第一操作模式中接收导致存储区域的导电类型的反转的第一电压，使得存储区域表现为读取区域的延伸，并且在第二操作模式 ，不会导致存储区域的反转的第二电压。

公开(公告)号：US20170059774A1

公开(公告)日：2017-03-02

申请号：US15051904

申请日：2016-02-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles Baudot

IPC: G02B6/122 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B2006/12097 ,  G02B2006/121 ,  G02F1/025

Abstract: An integrated circuit includes an active device for confinement of a light flux that is formed in a semiconducting substrate. A confinement rib is separated from two doped zones by two trenches. Each doped zone includes a contacting zone on an upper face. Each trench widens from a bottom wall towards the upper face of the corresponding doped zone. The widening trenches present a sidewall having a tiered profile between the trench and the doped zone. An opposite sidewall presents a straight profile.

Abstract translation: 集成电路包括用于限制形成在半导体衬底中的光束的有源器件。 限制肋通过两个沟槽与两个掺杂区分离。 每个掺杂区包括在上表面上的接触区。 每个沟槽从底壁朝向相应掺杂区的上表面变宽。 加宽的沟槽具有在沟槽和掺杂区域之间具有分层轮廓的侧壁。 相对的侧壁呈直线轮廓。

公开(公告)号：US09531979B2

公开(公告)日：2016-12-27

申请号：US14585704

申请日：2014-12-30

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Frédéric Lalanne ,  Christophe Mandier

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/378 ,  H04N5/374 ,  H04N5/3745

CPC classification number: H04N5/378 ,  H04N5/374 ,  H04N5/3745

Abstract: An IC image sensor device may include image sensing IC pixels arranged in an array, and pixel line pairs coupled to the image sensing IC pixels. The IC image sensor device may include circuitry coupled to the pixel line pairs and configured to operate the array in a global shutter mode. Each pair of the pixel line pairs may include a pair of spaced electrical conductors having a twist.

Abstract translation: IC图像传感器装置可以包括以阵列布置的图像感测IC像素，以及耦合到图像感测IC像素的像素线对。 IC图像传感器设备可以包括耦合到像素线对并被配置为以全局快门模式操作阵列的电路。 每对像素线对可以包括具有扭曲的一对间隔的电导体。

公开(公告)号：US09525019B2

公开(公告)日：2016-12-20

申请号：US14036519

申请日：2013-09-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Gros-Jean

IPC: H01G4/06 ,  H01G4/20 ,  H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  H01G4/08 ,  H01G4/12 ,  H01G4/33 ,  H01L21/02

CPC classification number: H01L28/40 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45542 ,  H01G4/085 ,  H01G4/1209 ,  H01G4/33 ,  H01L21/02189 ,  H01L21/02274 ,  H01L21/0228 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/435

Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.

Abstract translation: 一种制造在两个金属电极之间具有多晶介质层的电容器。 电介质层由金属电极之一上的介电金属氧化物的多晶生长形成。 在形成多晶电介质层期间，电介质氧化物的至少一个多晶生长条件被改变，这导致电介质氧化物在所述层的厚度内的多晶性质的变化。

公开(公告)号：US09522450B2

公开(公告)日：2016-12-20

申请号：US14221402

申请日：2014-03-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean Berthier ,  Lea Di Cioccio ,  Sebastien Mermoz

IPC: B23Q3/02 ,  H01L23/498 ,  H01L25/00

CPC classification number: B23Q3/02 ,  H01L23/49838 ,  H01L25/50 ,  H01L2224/26175 ,  H01L2224/95146 ,  H01L2924/0002 ,  Y10T29/49982 ,  Y10T29/49998 ,  Y10T29/53091 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A support is provided, including a reception zone in which the external envelope matches the shape of a plate configured to be placed on a droplet deposited at least in the reception zone in order to achieve capillary self-assembly of the plate and the support, and at least one pair of tracks that extend on the support from the reception zone and that have a lyophilic-type affinity with the droplet such that an overflow of the droplet beyond the reception zone is guided in the tracks, wherein the at least one pair of tracks includes a first track and a second track that do not have the same lyophilic-type degree of affinity with the droplet.

Abstract translation: 提供了一种支撑件，其包括接收区域，其中外部封套匹配被配置为放置在至少沉积在接收区域中的液滴上的板的形状，以便实现板和支撑件的毛细管自组装，以及 至少一对轨道，其在所述支撑体上从所述接收区域延伸并且具有与所述液滴的亲液亲和性，使得所述液滴超过所述接收区域的溢出被引导到所述轨道中，其中所述至少一对 轨道包括与液滴不具有相同的亲液亲和度的第一轨道和第二轨迹。

公开(公告)号：US20160366758A1

公开(公告)日：2016-12-15

申请号：US14956512

申请日：2015-12-02

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Nicolas HOTELLIER ,  François GUYADER ,  Vincent FIORI ,  Richard FOURNEL ,  Frédéric GIANESELLO

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K1/18

CPC classification number: H05K1/0216 ,  H01L21/762 ,  H01L21/7624 ,  H01L21/764 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2924/00014 ,  H05K1/111 ,  H05K1/181 ,  H05K3/0011 ,  H01L2224/05599

Abstract: An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.

Abstract translation: 电子设备具有背板，其包括基板后层，基板前层和介于基板后层与前层之间的电介质中间层。 电子结构位于基板前层上，并且包括电子部件和电连接。 基板后层包括固体局部区域和中空的局部区域。 中空的局部区域在所有基板后层上延伸。 基板后层不覆盖与中空的局部区域对应的介电中间层的至少一个局部区域。

公开(公告)号：US09478570B2

公开(公告)日：2016-10-25

申请号：US14929077

申请日：2015-10-30

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Robert Manouvrier ,  Pascal Fonteneau ,  Xavier Montagner

IPC: H01L27/146 ,  H01L29/423

CPC classification number: H01L27/14614 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/4236

Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.

公开(公告)号：US09460923B2

公开(公告)日：2016-10-04

申请号：US14220406

申请日：2014-03-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Aomar Halimaoui ,  Jean-Michel Hartmann

IPC: H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L21/02694 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/1054

Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.

Abstract translation: 本公开涉及一种方法，涉及：通过在布置在衬底上的硅层上外延生长来形成应变硅锗层; 注入原子以使硅层和硅锗层的下部非晶化，而不使硅锗层的表面部分非晶化; 并进行退火，以至少部分地使硅锗层松弛并使硅锗层和硅层的下部重新结晶，使得硅层变成应变硅层。

公开(公告)号：US09453723B1

公开(公告)日：2016-09-27

申请号：US14754747

申请日：2015-06-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Patrick LeMaitre ,  Jean-Francois Carpentier

IPC: G01B11/26 ,  G01B11/27

CPC classification number: G01B11/27 ,  G01R31/31728 ,  G02B6/12019

Abstract: A method is for testing a photonic integrated circuit (IC) that includes a test structure having a test optical splitter, a test optical input, and first and second test optical outputs. A device under test (DUT) is coupled between the first test optical output and the first output of the test optical splitter. The deembedding structure includes a deembedding optical splitter, a deembedding optical input and first and second deembedding optical outputs. The method includes coupling a test probe device to the test optical inputs and outputs and the deembedding optical inputs and outputs and operating the test probe device to make at least one test measurement related to the DUT and at least one deembedding measurement. The at least one test measurement is processed with the at least one deembedding measurement to determine whether the DUT is acceptable and independent of alignment error.

Abstract translation: 一种用于测试包括具有测试光分路器，测试光输入以及第一和第二测试光输出的测试结构的光子集成电路（IC）的方法。 被测设备（DUT）耦合在第一测试光输出端和测试光分路器的第一输出端之间。 该装饰结构包括一个嵌入式光分路器，一个嵌入式光输入端和第一和第二嵌入式光输出端。 该方法包括将测试探针装置耦合到测试光输入和输出以及去嵌入光输入和输出，并操作测试探针装置以进行至少一个与DUT相关的测试测量和至少一个去镶嵌测量。 用至少一个去镶嵌测量来处理至少一个测试测量，以确定DUT是否可接受并且不依赖于对准误差。