公开(公告)号：US09105559B2

公开(公告)日：2015-08-11

申请号：US14028517

申请日：2013-09-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Nathaniel Berliner ,  Hyun-Jin Cho ,  Johnathan Faltermeier ,  Kam-Leung Lee ,  Tenko Yamashita

IPC: H01L21/00 ,  H01L21/18 ,  H01L21/225

CPC classification number: H01L21/18 ,  H01L21/2236 ,  H01L21/2251 ,  H01L21/845 ,  H01L29/66803

Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFET fins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.

Abstract translation: 在包括NFET鳍片和PFET鳍片的半导体衬底上的FinFET器件的共形掺杂工艺。 在第一示例性实施例中，N型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将N型掺杂剂从N型掺杂剂组合物驱动到NFET鳍中。 P型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将P型掺杂剂从P型掺杂剂组合物驱动到PFET鳍中。 在第二示例性实施例中，NFET鳍和PFET鳍之一可以被第一掺杂剂组合物覆盖，然后第二掺杂剂组合物可以覆盖NFET鳍和PFET鳍，接着进行退火以在两种掺杂剂中驱动。

公开(公告)号：US10777465B2

公开(公告)日：2020-09-15

申请号：US15868199

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/51

Abstract: Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.

公开(公告)号：US10734499B2

公开(公告)日：2020-08-04

申请号：US15986031

申请日：2018-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/20 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088

Abstract: Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.

公开(公告)号：US10283423B2

公开(公告)日：2019-05-07

申请号：US15292184

申请日：2016-10-13

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC: H01L21/66 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

公开(公告)号：US10276659B2

公开(公告)日：2019-04-30

申请号：US15992431

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.

公开(公告)号：US20190103319A1

公开(公告)日：2019-04-04

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/088

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

公开(公告)号：US10249538B1

公开(公告)日：2019-04-02

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/311

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

公开(公告)号：US10249502B2

公开(公告)日：2019-04-02

申请号：US15004751

申请日：2016-01-22

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/336 ,  H01L21/285 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US10153201B2

公开(公告)日：2018-12-11

申请号：US15417848

申请日：2017-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc. ,  The Research Foundation for The State University of New York

Inventor： Huiming Bu ,  Hui-feng Li ,  Vijay Narayanan ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L23/485 ,  H01L29/08 ,  H01L27/092

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

公开(公告)号：US20180331040A1

公开(公告)日：2018-11-15

申请号：US16040752

申请日：2018-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L23/535 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/285 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.