公开(公告)号：US08878586B2

公开(公告)日：2014-11-04

申请号：US13863707

申请日：2013-04-16

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak ,  Kang-Yong Kim

IPC: H03L7/06 ,  H03K5/14 ,  G11C7/22 ,  H03L7/00 ,  G11C7/10 ,  H03L7/081

CPC classification number: H03L7/00 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract translation: 时钟同步系统和方法避免了高频时的输出时钟抖动，并且在粗略和精细延迟的边界处实现了平滑的相位转变。 该系统可以使用单个粗延迟线，其被配置为从输入参考时钟产生两个中间时钟并且在它们之间具有固定的相位差。 粗延迟线可以具有分层结构或非分层结构。 相位混合器接收这两个中间时钟并产生具有在中间时钟的相位之间的相位的最终输出时钟。 在高时钟频率下延迟线中的粗略移位不影响馈送到相位混频器中的中间时钟之间的相位关系。 来自相位混频器的输出时钟与输入参考时钟同步，即使在高时钟频率输入时也不会出现任何抖动或噪音。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US08862863B2

公开(公告)日：2014-10-14

申请号：US13951008

申请日：2013-07-25

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Jacob Robert Anderson ,  Huy Vo

IPC: G06F15/177 ,  G11C29/50 ,  G11C7/20 ,  G11C29/32 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C7/20 ,  G11C29/003 ,  G11C29/32 ,  G11C29/50012 ,  G11C2029/0407 ,  H01L25/0657

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract translation: 公开了设备，主 - 从检测电路，存储器和方法。 一种这样的方法包括执行主检测阶段，在此期间，将存储器组中的存储器单元确定为主存储器单元，在每个存储器单元处确定其相对于其他存储器单元的位置，以及在每个存储器单元处确定其位于 存储器组基于从属存储器单元的总数及其相对于其他存储器单元的位置。

公开(公告)号：US12300351B2

公开(公告)日：2025-05-13

申请号：US17823458

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G11C7/10 ,  G11C7/20

Abstract: Described apparatuses and methods relate to selectively disabling a die that may be included in a multiple-die package without necessarily disabling all the remaining dies within the package. A nonvolatile circuit, such as one or more fuses, may be included within individual dies and/or otherwise incorporated within the package. The nonvolatile circuit maintains a value for the die that is indicative of the operability of the die. Die disablement logic is operatively coupled to the nonvolatile circuit and can disable the die based on the value indicating that the die is unusable. The disabling of the die by the die disablement logic may be controlled by an override signal that allows the disabling or prevents the logic from disabling the die. Thus, the die disablement logic can prevent a defective die from functioning, but the die disablement logic may be overridden for testing or debugging.

公开(公告)号：US12260098B2

公开(公告)日：2025-03-25

申请号：US17944572

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yu-Sheng Hsu ,  Kang-Yong Kim ,  Ke Wei Chan

IPC: G06F3/06

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

公开(公告)号：US20250068345A1

公开(公告)日：2025-02-27

申请号：US18743783

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He ,  Kang-Yong Kim ,  Randall J. Rooney ,  Dong Pan

IPC: G06F3/06

Abstract: Apparatuses and methods per-row count based refresh target identification. A memory device stores count values associated with the word lines. An aggressor detector circuit stores a maximum of the count values and a row address associated with the maximum count value. Responsive to a targeted refresh signal, the stored count value is compared to a threshold. If the count value has crossed the threshold, then a targeted refresh operation may be performed on one or more refresh addresses based on the stored address, and the count value may be reset.

公开(公告)号：US20250060898A1

公开(公告)日：2025-02-20

申请号：US18938866

申请日：2024-11-06

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Kang-Yong Kim

IPC: G06F3/06

Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

公开(公告)号：US12176061B2

公开(公告)日：2024-12-24

申请号：US18420404

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US20240379148A1

公开(公告)日：2024-11-14

申请号：US18659305

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He ,  Kang-Yong Kim

IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/4076

Abstract: Apparatuses and techniques for implementing aspects of a time-varying threshold for usage-based disturbance mitigation. In an example aspect, usage-based disturbance circuitry of a memory device utilizes a threshold that varies over time for detecting conditions associated with usage-based disturbance. By utilizing the time-varying threshold, the usage-based disturbance circuitry can reduce a probability of a waterfall event causing a denial-of-service (DOS) situation. In particular, the time-varying threshold can spread out the refreshing of rows over a longer time period. This enables the memory device to have sufficient resources to service other memory requests while also mitigating usage-based disturbance. In example implementations, the threshold is at least partially randomized, which can make it challenging for a malicious actor to identify and overcome the usage-based disturbance mitigation techniques. Also, techniques for generating the time-varying threshold can be implemented without appreciably increasing a size or cost of the memory device.

公开(公告)号：US20240363191A1

公开(公告)日：2024-10-31

申请号：US18634096

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He ,  Kang-Yong Kim ,  Dong Pan

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G11C29/789

Abstract: Apparatuses and techniques for implementing usage-based disturbance (UBD) counter repair are described. In example implementations, a memory device includes multiple memory rows, multiple corresponding UBD counters, a register, and a spare UBD counter. If a UBD counter is faulty, logic can substitute the spare UBD counter. To do so, the logic can store a row address corresponding to the faulty UBD counter in the register. The logic can increment a value in the spare UBD counter responsive to a row activation corresponding to the stored row address. A mitigation procedure on a row that may be affected by the activation can be performed based on the value. A host device can control, at least partially, the UBD counter repair process. In these manners, a repair of a faulty UBD counter can be accomplished faster and/or with fewer resources as compared to replacing a memory row and corresponding UBD counter.

公开(公告)号：US20240312499A1

公开(公告)日：2024-09-19

申请号：US18672339

申请日：2024-05-23

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Yang Lu

IPC: G11C7/10 ,  H03K19/017 ,  H03K19/173

CPC classification number: G11C7/109 ,  G11C7/1087 ,  H03K19/01742 ,  H03K19/1737

Abstract: The subject application is directed to die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.