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    Multi-primary and distributed secondary transformer for power amplifier systems
    171.
    发明授权
    Multi-primary and distributed secondary transformer for power amplifier systems 有权
    用于功率放大器系统的多主分布式二次变压器

    公开(公告)号：US07940152B1

    公开(公告)日：2011-05-10

    申请号：US12785020

    申请日：2010-05-21

    Applicant: Woonyun Kim ,  Jihwan Kim ,  Chang-Ho Lee ,  Joy Laskar

    Inventor： Woonyun Kim ,  Jihwan Kim ,  Chang-Ho Lee ,  Joy Laskar

    IPC: H01F27/28

    CPC classification number: H01F19/04 ,  H03F3/195 ,  H03F3/24 ,  H03F2200/09 ,  H03F2200/451 ,  H03F2200/541 ,  H03F2200/543

    Abstract: A multi-primary and distributed transformer is provided for one or more sets of parallel-connected or series-connected power amplifiers. The transformer may include a plurality of primary windings, including a first primary winding, a second primary winding, a third primary winding, and a fourth primary winding, where each of the plurality of primary windings is not directly connected to any other of the plurality of primary windings, where each primary winding includes a respective positive port and a negative port for receiving respective differential signals, where each primary winding include a respective first number of turns; and a single secondary winding having a plurality of segments, including a first segment and a second segment, where each segment includes a second number of turns, the second number of turns greater than or equal to the respective first number of turns, where the single secondary winding includes at least one output port.

    Abstract translation: 为一组或多组并联或串联连接的功率放大器提供了一个多主分布式变压器。 变压器可以包括多个初级绕组，包括第一初级绕组，第二初级绕组，第三初级绕组和第四初级绕组，其中多个初级绕组中的每一个不直接连接到多个初级绕组中的任何另一个 的初级绕组，其中每个初级绕组包括相应的正端口和用于接收相应的差分信号的负端口，其中每个初级绕组包括相应的第一圈数; 以及具有多个段的单个次级绕组，其包括第一段和第二段，其中每个段包括第二匝数，第二匝数大于或等于相应的第一匝数，其中单个 次级绕组包括至少一个输出端口。

    Systems, methods, and apparatuses for high power complementary metal oxide semiconductor (CMOS) antenna switches using body switching and substrate junction diode controlling in multistacking structure
    172.
    发明授权
    Systems, methods, and apparatuses for high power complementary metal oxide semiconductor (CMOS) antenna switches using body switching and substrate junction diode controlling in multistacking structure 有权
    在多层结构中使用体开关和衬底结二极管控制的大功率互补金属氧化物半导体（CMOS）天线开关的系统，方法和装置

    公开(公告)号：US07843280B2

    公开(公告)日：2010-11-30

    申请号：US11943378

    申请日：2007-11-20

    Applicant: Minsik Ahn ,  Chang-Ho Lee ,  Jaejoon Chang ,  Wangmyong Woo ,  Haksun Kim ,  Joy Laskar

    Inventor： Minsik Ahn ,  Chang-Ho Lee ,  Jaejoon Chang ,  Wangmyong Woo ,  Haksun Kim ,  Joy Laskar

    IPC: H01P1/15 ,  H04B1/44

    CPC classification number: H03K17/693 ,  H03K17/102 ,  H03K2217/0018 ,  H04B1/48

    Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and source and body connection along with body floating technique to block high power signals from the transmit path by preventing channel formation of the device in OFF state as well as to maintain low insertion loss at the receiver path. Example embodiments of the CMOS antenna switch may provide for 35 dBm P 1 dB at both bands (e.g., 900 MHz and 1.9 GHz and 2.1 GHz). In addition, a −60 dBc second and third harmonic up to 28 dBm input power to the switch, may be obtained according to example embodiments of the invention.

    Abstract translation: 本发明的实施例可以提供可被称为CMOS SPDT开关的CMOS天线开关。 根据本发明的实施例，CMOS天线开关可以以多个频率操作，可能约为900MHz 1.9GHz和2.1GHz。 CMOS天线开关可以包括接收器开关和发送开关。 接收器开关可以利用具有主体衬底切换和源和体连接以及身体浮动技术的多堆叠晶体管，以通过防止器件在OFF状态下的通道形成以及保持低插入来阻止来自发射路径的高功率信号 在接收机路径损失。 CMOS天线开关的示例实施例可以在两个频带（例如，900MHz和1.9GHz和2.1GHz）处提供35dBm的P 1dB。 此外，根据本发明的示例性实施例，可以获得高达28dBm的输入功率对于开关的-60dBc的二次和三次谐波。

    FRACTIONAL RESOLUTION INTEGER-N FREQUENCY SYNTHESIZER
    175.
    发明申请
    FRACTIONAL RESOLUTION INTEGER-N FREQUENCY SYNTHESIZER 审中-公开
    分数分解整数N频率合成器

    公开(公告)号：US20100073052A1

    公开(公告)日：2010-03-25

    申请号：US12563790

    申请日：2009-09-21

    Applicant: Jaehyouk Choi ,  Jongmin Park ,  Kyutae Lim ,  Chang-Ho Lee ,  Haksun Kim ,  Joy Laskar

    Inventor： Jaehyouk Choi ,  Jongmin Park ,  Kyutae Lim ,  Chang-Ho Lee ,  Haksun Kim ,  Joy Laskar

    IPC: H03L7/08

    CPC classification number: H03L7/185 ,  H03L7/0891 ,  H03L2207/10

    Abstract: Embodiments of the invention may provide for a frequency synthesizer capable to generate an output signal in which the frequency is a fractional portion of the reference frequency without a fractional divider. Based on mathematical relationship (“relatively prime”) between the reference frequency and other injection frequencies mixed with the output signal of a voltage controlled oscillator, the synthesizer is able to generate signals evenly spaced in the frequency domain like Fractional-N PLLs. The synthesizer may include an Integer-N PLL, a SSB mixer, frequency dividers, and frequency multipliers. A Integer-N PLL may include a Phase and Frequency Detector, a Charge Pump, a Loop Filter and a Dual Modulus Divider. By not requiring a fractional divider, the frequency synthesizer is able to avoid adopting any compensation circuits such as Sigma-Delta modulator to suppress fractional spurs. Therefore, the chip area, power consumption and complexity will be reduced considerably.

    Abstract translation: 本发明的实施例可以提供能够产生输出信号的频率合成器，其中频率是参考频率的小数部分而没有分数分频器。 基于与压控振荡器的输出信号混合的参考频率和其他注入频率之间的数学关系（“相对主要”），合成器能够在频域中产生均匀间隔的信号，如分数N PLL。 合成器可以包括整数N PLL，SSB混频器，分频器和频率乘法器。 整数N PLL可以包括相位和频率检测器，电荷泵，环路滤波器和双模数分频器。 通过不需要分数分频器，频率合成器能够避免采用诸如Sigma-Delta调制器之类的任何补偿电路来抑制分数杂散。 因此，芯片面积，功耗和复杂度将大大降低。

    Systems, methods, and apparatuses for coarse spectrum-sensing modules
    176.
    发明授权
    Systems, methods, and apparatuses for coarse spectrum-sensing modules 失效
    用于粗糙频谱感测模块的系统，方法和装置

    公开(公告)号：US07668262B2

    公开(公告)日：2010-02-23

    申请号：US11458275

    申请日：2006-07-18

    Applicant: Wangmyong Woo ,  Chang-Ho Lee ,  Jungsuk Lee ,  Haksun Kim

    Inventor： Wangmyong Woo ,  Chang-Ho Lee ,  Jungsuk Lee ,  Haksun Kim

    IPC: H04L27/06

    CPC classification number: H04L27/2647 ,  H04B1/1027 ,  H04L27/0004 ,  H04L27/0006

    Abstract: Systems, methods, and apparatuses are provided for coarse-sensing modules that are operative for providing initial determinations of spectrum occupancy. The coarse-sensing modules may include a wavelet waveform generator providing a plurality of wavelet pulses, and a multiplier that combines the wavelet pulses with an input signal to form a correlation signal. The coarse sensing modules may further include an integrator that receives the generated correlation signal from the multiplier, where the integrator determines correlation values from integrating the correlation signal, and a spectrum recognition module in communication with the integrator that determines an available spectrum segment based at least in part on the correlation values. In addition, the spectrum recognition module may determine an available spectrum segment by utilizing information from a spectrum usage database, where the spectrum usage database includes information associated with one or more known signal types.

    Abstract translation: 提供了用于粗略感测模块的系统，方法和装置，其用于提供频谱占用的初始确定。 粗糙感测模块可以包括提供多个小波脉冲的小波波形发生器，以及将小波脉冲与输入信号组合以形成相关信号的乘法器。 粗略感测模块还可以包括积分器，其从乘法器接收所产生的相关信号，其中积分器确定来自积分相关信号的相关值，以及与积分器通信的频谱识别模块，该频谱识别模块至少基于确定可用频谱段 部分归因于相关值。 此外，频谱识别模块可以通过利用来自频谱使用数据库的信息来确定可用频谱段，其中频谱使用数据库包括与一个或多个已知信号类型相关联的信息。

    Systems, methods, and apparatuses for a long delay generation technique for spectrum-sensing of cognitive radios
    180.
    发明授权
    Systems, methods, and apparatuses for a long delay generation technique for spectrum-sensing of cognitive radios 失效
    用于认知无线电频谱感知的长延迟生成技术的系统，方法和装置

    公开(公告)号：US07528751B2

    公开(公告)日：2009-05-05

    申请号：US11778557

    申请日：2007-07-16

    Applicant: Jongmin Park ,  Taejoong Song ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

    Inventor： Jongmin Park ,  Taejoong Song ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

    IPC: H03M1/00

    CPC classification number: H04B17/382

    Abstract: Embodiments of the invention may provide for a long delay generator for the spectrum sensing of cognitive radio systems. The long delay generator may include an Analog-to-Digital Converter (ADC), memory element, and Digital-to-Analog Converter (DAC). The memory element may utilize shift register bank or Random-Access Memory (RAM) cells. The long delay generator may provide for a selectable delay by digitizing the received signal, delaying the received signal in the digital domain, and reconstructing the delayed signal as an analog. The analog delayed signal may then be compared or otherwise correlated with the original input signal using an analog auto-correlation technique to determine whether a meaningful signal type has been identified or otherwise detected.

    Abstract translation: 本发明的实施例可以提供用于认知无线电系统的频谱感测的长延迟发生器。 长延迟发生器可以包括模数转换器（ADC），存储器元件和数模转换器（DAC）。 存储器元件可以利用移位寄存器组或随机存取存储器（RAM）单元。 长延迟发生器可以通过数字化接收的信号，延迟数字域中的接收信号，并将延迟的信号重建为模拟来提供可选择的延迟。 然后可以使用模拟自相关技术将模拟延迟信号与原始输入信号进行比较或相关，以确定是否已识别或以其他方式检测到有意义的信号类型。

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