公开(公告)号：US09749648B2

公开(公告)日：2017-08-29

申请号：US14038042

申请日：2013-09-26

Applicant: Socionext INC.

Inventor： Tatsushi Otsuka

IPC: H04N19/436 ,  H04N19/513

CPC classification number: H04N19/436 ,  H04N19/513

Abstract: A moving image processing apparatus has an encoder unit configured to include a plurality of encoders which respectively encode a plurality of divided images into which images of a moving image are divided in such a manner that each divided image includes an overlapped area to generate encoded divided image data; and a decoder unit configured to include a plurality of decoders which respectively decode the plurality of encoded divided image data inputted from the encoder unit and respectively extract information on motion vectors of the divided images; and a composition unit which blends a plurality of decoded divided images decoded and generated by the plurality of decoders respectively in the overlapped area to output the images of the moving image. And the composition unit determines a blend ratio of the overlapped area based on the information on the motion vectors.

公开(公告)号：US09748939B2

公开(公告)日：2017-08-29

申请号：US14984813

申请日：2015-12-30

Applicant: SOCIONEXT INC.

Inventor： Keiko Iwamoto ,  Tohru Mizutani ,  Takao Kono

IPC: H03B1/00 ,  H03K3/00 ,  H03K5/24 ,  H03K19/0175

CPC classification number: H03K5/24 ,  H03K19/017509

Abstract: An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

公开(公告)号：US09748237B2

公开(公告)日：2017-08-29

申请号：US15079987

申请日：2016-03-24

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H03K19/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6681 ,  H03K19/0013

Abstract: Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node. The second n-channel transistor is comprised of m fin transistors having the same gate length and the same gate width where m is greater than n, and has its gate connected to a second input node.

公开(公告)号：US20170221874A1

公开(公告)日：2017-08-03

申请号：US15493321

申请日：2017-04-21

Applicant: SOCIONEXT INC.

Inventor： Tooru MATSUI

IPC: H01L27/02 ,  H01L23/00 ,  H02H9/04 ,  H01L23/528

CPC classification number: H01L27/0248 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/5286 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0296 ,  H01L2224/06131 ,  H01L2924/0002 ,  H01L2924/14 ,  H02H9/046 ,  H01L2924/00

Abstract: Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.

公开(公告)号：US20170221825A1

公开(公告)日：2017-08-03

申请号：US15493338

申请日：2017-04-21

Applicant: SOCIONEXT INC.

Inventor： Tooru MATSUI ,  Masahiro YOSHIMURA

IPC: H01L23/528 ,  H01L23/60 ,  H02H9/04

CPC classification number: H01L23/5286 ,  H01L21/82 ,  H01L21/822 ,  H01L23/60 ,  H01L27/04 ,  H02H9/046

Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.

公开(公告)号：US09705475B2

公开(公告)日：2017-07-11

申请号：US15069878

申请日：2016-03-14

Applicant: SOCIONEXT INC.

Inventor： Ian Juso Dedic ,  David Timothy Enright

IPC: H03K3/00 ,  H03H11/22 ,  H03K5/15 ,  G06F1/10 ,  H01L49/02 ,  H01F17/00

CPC classification number: H03H11/22 ,  G06F1/10 ,  H01F2017/0073 ,  H01L28/10 ,  H03K5/1506

Abstract: An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase.

公开(公告)号：US09703730B2

公开(公告)日：2017-07-11

申请号：US14605678

申请日：2015-01-26

Applicant: SOCIONEXT INC.

Inventor： Yoshihiro Kubo

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1605 ,  G06F13/1626 ,  G06F13/1673 ,  G06F13/4022

Abstract: In an arbitration circuit, transactions output from a plurality of master circuits are stored in a first-in-first-out type first buffer, and when a high-priority transaction higher in priority than one of the stored transactions is output from one of the plural master circuits, a cancel request of a low-priority transaction lower in priority than the high-priority transaction, out of the stored transactions, is output to a second buffer in a slave circuit, and when the cancel request is successful, the high-priority transaction is output to the slave circuit, and after the high-priority transaction is output to the slave circuit, the low-priority transaction whose cancel request is successful is output to the slave circuit.

公开(公告)号：US09673769B2

公开(公告)日：2017-06-06

申请号：US15014621

申请日：2016-02-03

Applicant: SOCIONEXT INC.

Inventor： Takafumi Nasu ,  Shinichiro Uemura

IPC: H03F3/193 ,  H03G3/30 ,  H03F1/02 ,  H03G1/00 ,  H03F1/22 ,  H03F3/45 ,  H03F1/32

CPC classification number: H03G3/3036 ,  H03F1/0205 ,  H03F1/0277 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/45179 ,  H03F2200/451 ,  H03F2203/45306 ,  H03G1/0023 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/3052 ,  H03G3/3063

Abstract: A variable gain transconductance amplifier includes an amplifier transistor connected to an input node, a cascode transistor having a source connected to a drain of the amplifier transistor and having a drain connected to an output node, and a switching circuit connecting or disconnecting a node to which the amplifier transistor and the cascode transistor are connected to or from a fixed potential in a switchable manner. A variable gain circuit may include the variable gain transconductance amplifier.

公开(公告)号：US09672384B2

公开(公告)日：2017-06-06

申请号：US14091483

申请日：2013-11-27

Applicant: Socionext Inc.

Inventor： Seiji Goto ,  Jun Kamada ,  Taiji Tamiya

IPC: G06F11/30 ,  G06F12/14 ,  G06F21/70 ,  G06F21/52 ,  G06F21/55 ,  G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72

CPC classification number: G06F21/70 ,  G06F12/1027 ,  G06F12/1408 ,  G06F13/24 ,  G06F21/52 ,  G06F21/53 ,  G06F21/554 ,  G06F21/575 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72 ,  G06F21/74 ,  G06F2212/1052 ,  G06F2212/682

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

公开(公告)号：US09659119B2

公开(公告)日：2017-05-23

申请号：US14629910

申请日：2015-02-24

Applicant: Socionext, Inc.

Inventor： Furuna Yamamoto

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/08 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/82 ,  G06F2217/84

Abstract: When a design apparatus adjusts clock skews, the design apparatus separates each of the power supply currents which flow through circuit sections that operate in synchronization with a clock signal into a plurality of frequency components, sets skew values of the clock signal which reaches the circuit sections, and performs, by changing the skew values, repetition of calculating a combined amplitude by combining, with respect to each of the frequency components, corresponding ones of the frequency components of the power supply currents which flow through the circuit sections and finds dependence of the combined amplitude on a skew.