公开(公告)号：US12189304B2

公开(公告)日：2025-01-07

申请号：US17215676

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ching Lee ,  Yu-Piao Fang

IPC: G03F7/20 ,  G03F7/00 ,  G06T7/00 ,  G06T7/68

Abstract: A method includes forming a first material layer on a semiconductor wafer, the first material layer comprising a first periodic structure within an overlay mark region of the semiconductor wafer and forming a second material layer on the semiconductor wafer, the second material layer comprising a second periodic structure in the overlay mark region. The method further includes with an acoustic transmitter device disposed within the overlay mark region, transmitting an acoustic wave across both the first periodic structure and the second periodic structure. The method further includes, with an acoustic wave receiver device, detecting the acoustic wave and determining an overlay error between the first material layer and the second material layer based on the acoustic wave as detected by the acoustic wave receiver device.

公开(公告)号：US20250004383A1

公开(公告)日：2025-01-02

申请号：US18346113

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kenji YAMAZOE ,  Chih-Shiang CHOU

IPC: G03F7/00 ,  G03F1/70 ,  H01L21/033

Abstract: A process for forming a photolithography mask includes generating a sub-resolution assist feature (SRAF) pattern from a blank mask layout based on a target layout. The SRAF pattern can be generated using an iterative process including finding the gradient of a cost function. A main pattern can be generated simultaneously with the SRAF pattern or after generation of the SRAF pattern.

公开(公告)号：US12184283B2

公开(公告)日：2024-12-31

申请号：US17654803

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: H03K19/1776 ,  H03K19/20 ,  H10B99/00

Abstract: Structures and methods for the co-optimization of core (logic) devices and SRAM devices include a semiconductor device having a logic portion and a memory portion. In some embodiments, a logic device is disposed within the logic portion. In some cases, the logic device includes a single fin N-type FinFET and a single fin P-type FinFET. In some examples, a static random-access memory (SRAM) device is disposed within the memory portion. The SRAM device includes an N-well region disposed between two P-well regions, where the two P-well regions include an N-type FinFET pass gate (PG) transistor and an N-type FinFET pull-down (PD) transistor, and where the N-well region includes a P-type FinFET pull-up (PU) transistor.

公开(公告)号：US12183791B2

公开(公告)日：2024-12-31

申请号：US18309181

申请日：2023-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy Liaw

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H10B10/00

Abstract: An integrated circuit (IC) structure includes a substrate and a fin structure. The substrate includes a first cell region and a second cell region abutting the first cell region. The fin structure includes a first plan-view profile within the first cell region and a second plan-view profile within the second cell region. The first plan-view profile includes a first sidewall and a second sidewall opposing the first sidewall. The second plan-view profile includes a third sidewall and a fourth sidewall opposing the third sidewall. A width between the first sidewall and the second sidewall is greater than a width between the third sidewall and the fourth sidewall.

公开(公告)号：US12183736B2

公开(公告)日：2024-12-31

申请号：US18356802

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L27/07 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

公开(公告)号：US12183652B2

公开(公告)日：2024-12-31

申请号：US17884272

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy Liaw

IPC: H01L23/48 ,  H01L23/367 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/12

Abstract: An IC structure includes a plurality of first fins, a plurality of second fins, a plurality of first gate structures, a plurality of second gate structures, and a first gate contact. The first fins and the second fins are over a substrate. The first gate structures traverse the plurality of first fins. The second gate structures traverse the plurality of second fins. The first gate structures have a first gate pitch. The second gate structures have a second gate pitch wider than the first gate pitch. The first gate contact is over a first one of the second gate structures. The first gate contact overlaps a location where the first one of the second gate structures traverses across a first one of the second fins.

公开(公告)号：US12181797B2

公开(公告)日：2024-12-31

申请号：US17483302

申请日：2021-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Ping-Hsun Lin ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F7/004 ,  H01L21/033

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a multi-layer patterned absorber layer on the reflective multilayer stack is provided. Disclosed embodiments include an absorber layer that includes an alloy comprising ruthenium (Ru), chromium (Cr), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), tungsten (W) or palladium (Pd), and at least one alloying element. The at least one alloying element includes ruthenium (Ru), chromium (Cr), tantalum (Ta), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), hafnium (Hf), boron (B), nitrogen (N), silicon (Si), zirconium (Zr) or vanadium (V). Other embodiments include a multi-layer patterned absorber structure with layers that include an alloy and an alloying element, where at least two of the layers of the multi-layer structure have different compositions.

公开(公告)号：US20240427081A1

公开(公告)日：2024-12-26

申请号：US18401851

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ning Weng ,  Yu-Ming Chou ,  Shih Wei Liang ,  Nien-Fang Wu ,  Jiun Yi Wu ,  Chen-Hua Yu

IPC: G02B6/122 ,  G02B6/136

Abstract: Optical devices and methods of manufacture are presented herein. In an embodiment, an optical device is provided that includes a first substrate, the first substrate including an optical device layer, and a semiconductor die, a first waveguide structure over the first substrate, the first waveguide structure including a first optical component surrounded by cladding material, wherein the first waveguide structure has a top surface, the top surface including a first portion at a first distance from the first substrate, a second portion at a second distance from the first substrate, and a transition portion between the first portion to the second portion, wherein the second distance is greater than the first distance, and a first reflective structure over the first portion and the transition portion, wherein a portion of the first reflective structure over the transition portion is a curved surface.

公开(公告)号：US12176415B2

公开(公告)日：2024-12-24

申请号：US17814756

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

公开(公告)号：US12176372B2

公开(公告)日：2024-12-24

申请号：US17197291

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Ming-Che Lee

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards a pixel sensor. The pixel sensor includes a substrate having a front-side opposite a back-side. An image sensor element comprises an active layer disposed within the substrate, where the active layer comprises germanium. An anti-reflective coating (ARC) structure overlies the back-side of the substrate. The ARC structure includes a first dielectric layer overlying the back-side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer. A first index of refraction of the first dielectric layer is less than a second index of refraction of the second dielectric layer, and a third index of refraction of the third dielectric layer is less than the first index of refraction.