公开(公告)号：US11742423B2

公开(公告)日：2023-08-29

申请号：US17761510

申请日：2020-08-20

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jing Zhu ,  Guichuang Zhu ,  Nailong He ,  Sen Zhang ,  Shaohong Li ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095

Abstract: A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.

公开(公告)号：US20230215503A1

公开(公告)日：2023-07-06

申请号：US17928333

申请日：2021-04-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Ming GU ,  Hao WANG ,  Shuming GUO ,  Youhui LI ,  Bin CHEN ,  Yongqiang HU

IPC: G11C16/28 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/28 ,  G11C16/08 ,  G11C16/30

Abstract: A semiconductor memory comprising: a comparison readout circuit comprising a first port configured to receive an electric signal of a read memory unit and a second port configured to receive a reference electric signal, the comparison readout circuit being configured to compare the electric signal of the read memory unit with the reference electric signal to obtain storage information of the memory unit; and a first/second column decoder connected to a first/second memory array and the comparison readout circuit and configured to select a bitline corresponding to the read memory unit when a memory array selection signal enables the first/second memory array, and output the electric signal of the memory unit to the first port by means of the bitline, and further configured to connect a first bitline of the first/second memory array to the second port when the memory array selection signal does not enable the first/second memory array.

公开(公告)号：US11671765B2

公开(公告)日：2023-06-06

申请号：US17422300

申请日：2020-04-30

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yonggang Hu ,  Guoping Zhou ,  Changfeng Xia

IPC: H04R19/00 ,  H04R19/04 ,  B81B7/02

CPC classification number: H04R19/04 ,  B81B7/02 ,  H04R19/005 ,  B81B2201/0257 ,  B81B2203/0127 ,  H04R2201/003

Abstract: A Micro-Electro-Mechanical System (MEMS) device includes a substrate, and a first sacrificial layer, a first conductive film, a second sacrificial layer, and a second conductive film successively laminated on the substrate, the second sacrificial layer being provided with a cavity; and further includes an amplitude-limiting layer provided with a first through hole and an isolation layer provided with a second through hole. The amplitude-limiting layer is located between the first conductive film and the first sacrificial layer and the isolation layer is located between the amplitude-limiting layer and the first conductive film, and/or the amplitude-limiting layer is located on the second conductive film and the isolation layer is located between the amplitude-limiting layer and the second conductive film. The amplitude-limiting layer extends to a projection region of an opening of the cavity and is in a suspended state.

公开(公告)号：US20230146299A1

公开(公告)日：2023-05-11

申请号：US17912760

申请日：2021-07-02

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jingchuan ZHAO ,  Nailong HE ,  Sen ZHANG ,  Zhili ZHANG ,  Hao WANG

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/66681

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the LDMOS device are disclosed. The device includes: a substrate (101) having a second conductivity type; a drift region (102) that has a first conductivity type and is disposed on the substrate (101), wherein the first conductivity type is opposite to the second conductivity type; a plurality of layers of doped structures disposed in the drift region (102), each layer of the doped structure comprising at least one doped bar (105) extending in a lengthwise direction of a conductive channel; and a plurality of doped polysilicon pillars (106) disposed in the drift region (102) so as to extend downward through the doped bar (105) of at least one of the layer of doped structures, wherein ions doped in the doped polysilicon pillars (106) and ions doped in the doped bar have opposite conductivity types.

公开(公告)号：US20230095590A1

公开(公告)日：2023-03-30

申请号：US17799459

申请日：2020-12-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Youhui LI ,  Lijuan ZHU

IPC: G05F3/24 ,  G11C16/30

Abstract: A bias current generation circuit and a flash memory. The bias current generation circuit includes a voltage source, a switching circuit and a current generation circuit. The voltage source is configured to provide a voltage for generating a bias current. An input terminal of the switching circuit is connected to the voltage source, a control terminal of the switching circuit is configured to receive a control signal. The current generation circuit includes a first MOS transistor and a second MOS transistor, an input terminal and a control terminal of the first MOS transistor are connected to an output terminal of the switching circuit, an output terminal of the first MOS transistor is connected to an input terminal and a control terminal of the second MOS transistor, and an output terminal of the second MOS transistor is grounded.

公开(公告)号：US20230019004A1

公开(公告)日：2023-01-19

申请号：US17762206

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiaxing WEI ,  Qichao WANG ,  Kui XIAO ,  Dejin WANG ,  Li LU ,  Ling YANG ,  Ran YE ,  Siyang LIU ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/78

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

公开(公告)号：US20220384641A1

公开(公告)日：2022-12-01

申请号：US17886609

申请日：2022-08-12

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN ,  Feng LIN ,  Shuxian CHEN

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/266

Abstract: A method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a semiconductor substrate of a first conductivity type, forming a deep well of a second conductivity type in the semiconductor substrate, forming a channel region of the first conductivity type, a first well region of the first conductivity type, and a drift region of the second conductivity type in the deep well, the first well region and the channel region being spaced by a portion of the deep well, the drift region being located between the channel region and the first well region, forming an ion implantation region of the first conductivity type in the deep well, the ion implantation region being located under the drift region, and forming a source region of the second conductivity type and a drain region of the second conductivity type in the deep well.

公开(公告)号：US20220359673A1

公开(公告)日：2022-11-10

申请号：US17623485

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jingchuan ZHAO ,  Zhili ZHANG ,  Sen ZHANG

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: A laterally diffused metal oxide semiconductor device and a manufacturing method thereof. The device includes: a substrate of a second conductivity type; a drift region arranged on the substrate and of a first conductivity type; a source region of the first conductivity type; a drain region of the first conductivity type; and a longitudinal floating field plate structure arranged between the source region and the drain region and including a dielectric layer arranged on an inner surface of a trench and polysilicon filling the trench. The trench extends from an upper surface of the drift region downward through the drift region into the substrate. At least two longitudinal floating field plate structures are provided, and at least two of the longitudinal floating field plate structures are located at different positions in a length direction of a conductive channel.

公开(公告)号：US11476324B2

公开(公告)日：2022-10-18

申请号：US17263285

申请日：2019-11-11

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Hongfeng Jin

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/311

Abstract: An MIM capacitor and a manufacturing method therefor. The manufacturing method comprises: providing a semiconductor substrate, and forming a first metal layer on the semiconductor substrate; forming an anti-reflection layer on the first metal layer; performing photoetching and etching on the first metal layer and the anti-reflection layer so as to define an MIM capacitor region, wherein the first metal layer in the MIM capacitor region serves as a lower electrode plate of the MIM capacitor, and the anti-reflection layer in the MIM capacitor region serves as a dielectric layer of the MIM capacitor; and forming an upper electrode plate of the MIM capacitor on the anti-reflection layer in the MIM capacitor region.

公开(公告)号：US20220302305A1

公开(公告)日：2022-09-22

申请号：US17639359

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong HE

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/266 ,  H01L21/265

Abstract: The present disclosure provides a lateral double-diffused metal oxide semiconductor device and a manufacturing method thereof, and an electronic apparatus. The method includes: providing a semiconductor substrate, and forming a drift region and a body region in the semiconductor substrate; forming a drain region in the drift region, forming a source region in the body region, and forming, on the body region, a gate structure extending to the drift region; implanting ions of a first type, so as to form, at a bottom of the drift region, first ion implantation regions extending along a direction from the gate structure to the drain region; forming, above the first ion implantation regions, a plurality of mutually spaced deep trench structures and fin structures between adjacent ones of the deep trench structures; and implanting ions of a second type in the deep trench structures to form second ion implantation regions.