公开(公告)号：US10418484B1

公开(公告)日：2019-09-17

申请号：US15920748

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Edward J. Nowak ,  Julien Frougier ,  Jia Zeng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/8232 ,  H01L27/112 ,  H01L27/24 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/786

Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.

公开(公告)号：US10418365B2

公开(公告)日：2019-09-17

申请号：US16111263

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3205 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

公开(公告)号：US10418364B2

公开(公告)日：2019-09-17

申请号：US15252995

申请日：2016-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Jürgen Thees

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L21/768 ,  H01L23/485 ,  H01L27/06

Abstract: A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode.

公开(公告)号：US20190280105A1

公开(公告)日：2019-09-12

申请号：US15916323

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Qun Gao ,  Jerome Ciavatti ,  Yi Qi ,  Wei Hong ,  Yongjun Shi ,  Jae Gon Lee ,  Chun Yu Wong

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

公开(公告)号：US10411832B2

公开(公告)日：2019-09-10

申请号：US15336974

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Yang Liu ,  Jilei Yin ,  Wei Jiang

IPC: H04L1/00

Abstract: Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.

公开(公告)号：US20190273148A1

公开(公告)日：2019-09-05

申请号：US16415519

申请日：2019-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US20190273028A1

公开(公告)日：2019-09-05

申请号：US15910603

申请日：2018-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/762

Abstract: Structures and methods associated with a silicon-on-insulator substrate are needed. A silicon-on-insulator substrate is provided that includes a device layer of single-crystal semiconductor material, a buried oxide layer, a handle wafer of single-crystal semiconductor material, and a non-single-crystal semiconductor layer between the handle wafer and the buried oxide layer. A trench is formed that extends through the device layer, the buried oxide layer, and the non-single-crystal semiconductor layer to the handle wafer. A semiconductor layer is epitaxially grown from the handle wafer to at least partially fill the trench, and a device structure is formed using at least a portion of the semiconductor layer.

公开(公告)号：US20190271918A1

公开(公告)日：2019-09-05

申请号：US15909071

申请日：2018-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Guoxiang Ning ,  Meixiong Zhao ,  Erfeng Ding

IPC: G03F7/20 ,  H01L21/308

Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.

公开(公告)号：US10403629B2

公开(公告)日：2019-09-03

申请号：US15804556

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul

IPC: H01L27/11 ,  H01L27/092 ,  G11C11/412 ,  H01L27/118

Abstract: One illustrative 6T SRAM cell structure disclosed herein includes a first active region with a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which are formed in and above the first active region, wherein the first N-type pull-down transistor is positioned laterally between the first N-type pass gate transistor and the first P-type pull-up transistor, and a second active region with a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which are formed in and above the second active region, wherein the second N-type pull-down transistor is positioned laterally between the second N-type pass gate transistor and the second P-type pull-up transistor.

公开(公告)号：US10403548B2

公开(公告)日：2019-09-03

申请号：US15811965

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hong Yu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: The disclosure relates to integrated circuit (IC) structures with a single diffusion break (SDB) and end isolation regions, and methods of forming the same after forming a metal gate. A structure may include: a plurality of fins positioned on a substrate; a plurality of metal gates each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of metal gates; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins; an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of metal gates; and an insulator cap positioned on an upper surface of at least a portion of one of the plurality of metal gates.