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公开(公告)号：US11996849B2
公开(公告)日：2024-05-28
申请号：US18176753
申请日：2023-03-01
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
CPC classification number: H03K5/15066 , H03K5/15093 , H03L7/0996
Abstract: In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register
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公开(公告)号：US11973457B2
公开(公告)日：2024-04-30
申请号：US17323602
申请日：2021-05-18
Applicant: STMicroelectronics S.r.l. , STMicroelectronics Application GMBH , STMicroelectronics (Alps) SAS
Inventor： Aldo Occhipinti , Christophe Roussel , Fritz Burkhardt , Ignazio Testoni
IPC: H02P3/18 , E05F15/60 , H02P6/16 , H02P7/03 , H02P7/29 , H03K3/037 , H03K17/687 , B60J5/10 , B60R16/033
CPC classification number: H02P7/04 , E05F15/60 , H02P7/29 , H03K3/0377 , H03K17/6871 , B60J5/10 , B60R16/033 , E05Y2201/434 , E05Y2900/548 , H03K2217/0063 , H03K2217/0072 , H03K2217/0081
Abstract: An embodiment driver circuit comprises a power supply pin configured to receive a power supply voltage, and a set of control pins configured to provide a set of control signals for controlling switching of a set of switches of an h-bridge circuit comprising a pair of high-side switches and a pair of low-side switches. The driver circuit comprises control circuitry coupled to the control pins and configured to generate the control signals, and sensing circuitry coupled to the power supply pin and configured to generate a detection signal indicative of the power supply voltage exceeding a threshold value. The control circuitry is sensitive to the detection signal and is configured to generate the control signals to activate one of the pair of high-side switches and the pair of low-side switches and de-activate the other of the pair of high-side switches and the pair of low-side switches.
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公开(公告)号：US20240134406A1
公开(公告)日：2024-04-25
申请号：US18379262
申请日：2023-10-11
Inventor： Julien GOULIER , Nicolas GOUX , Marc JOISSON
CPC classification number: G05F3/262 , G05F1/468 , H03K17/18 , H03K17/22 , H03F3/45179
Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.
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公开(公告)号：US20240096412A1
公开(公告)日：2024-03-21
申请号：US18464093
申请日：2023-09-08
Applicant: STMICROELECTRONICS S.r.l. , STMICROELECTRONICS (ALPS) SAS
Inventor： Antonino CONTE , Agatino Massimo MACCARRONE , Francesco TOMAIUOLO , Thomas JOUANNEAU , Vincenzo RUSSO
IPC: G11C13/00 , H03K19/0185 , H03K19/20
CPC classification number: G11C13/0028 , G11C13/0004 , H03K19/018521 , H03K19/20
Abstract: In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.
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公开(公告)号：US11914718B2
公开(公告)日：2024-02-27
申请号：US17657027
申请日：2022-03-29
Inventor： Franck Albesa , Nicolas Anquet
IPC: G06F21/57 , G06F9/4401 , G06F21/60
CPC classification number: G06F21/575 , G06F9/4403 , G06F21/602 , G06F2221/034
Abstract: The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
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Patent Agency Ranking
公开(公告)号：US20240006896A1
公开(公告)日：2024-01-04
申请号：US18346494
申请日：2023-07-03
Inventor： Patrick Arnould , Alexandre Tramoni
IPC: H02J7/00
CPC classification number: H02J7/0031 , H02J7/0063
Abstract: In accordance with an embodiment, a circuit for managing a power supply of an electronic module includes: a first state machine configured to receive a first command for disabling the module, and to verify that the first command remains the same for a first minimum time period; and a second state machine configured to cut off a power supply of a first portion of the module when the second state machine receives a second command from the first state machine indicating that the first command has remained the same for the first minimum time period. The first portion of the module is configured to is configured to be powered from a battery via a first power supply voltage.
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公开(公告)号：US20230333581A1
公开(公告)日：2023-10-19
申请号：US18296068
申请日：2023-04-05
Applicant: STMicroelectronics (ALps) SAS
Inventor： Vratislav Michal
Abstract: An integrated circuit includes a temperature-independent voltage generating circuit configured to generate a bandgap voltage by summing a voltage proportional to absolute temperature and a voltage complementary to absolute temperature, a temperature threshold detection circuit including a resistive voltage divider bridge configured to generate a reference voltage equal to a fraction of the bandgap voltage and a comparator circuit configured to compare the voltage proportional to absolute temperature with the reference voltage.
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188.发明公开公开(公告)号：US20230291645A1
公开(公告)日：2023-09-14
申请号：US18321516
申请日：2023-05-22
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , H04L41/0803
CPC classification number: H04L41/0813 , H04L49/109 , G06F15/17306 , G06F15/177 , H04L41/0803 , G06F21/85
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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公开(公告)号：US20230291395A1
公开(公告)日：2023-09-14
申请号：US18176753
申请日：2023-03-01
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
CPC classification number: H03K5/15066 , H03K5/15093 , H03L7/0996
Abstract: In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register
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190.发明公开公开(公告)号：US20230283252A1
公开(公告)日：2023-09-07
申请号：US18116124
申请日：2023-03-01
Applicant: STMicroelectronics (Alps) SAS
Inventor： Kuno LENZ
IPC: H03F3/45
CPC classification number: H03F3/45475 , H03F2200/375 , H03F2203/45212
Abstract: An internal voltage offset between a positive input and a negative input of a first operational amplifier is compensated. The negative input and the positive input of the first operational amplifier are coupled at the same voltage level. A comparison current generated at an output of the first operational amplifier has a sign that is representative of a sign of the internal voltage offset. The output of the first operational amplifier is biased to a threshold voltage using a current-to-voltage converter. A control voltage is generated from a sum of the threshold voltage and a voltage conversion of the comparison current. Compensation for the internal voltage offset between the positive and negative inputs of the first operational amplifier is made dependent on the control voltage.
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