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公开(公告)号：US09257420B2
公开(公告)日：2016-02-09
申请号：US14171931
申请日：2014-02-04
Applicant: STMicroelectronics (Tours) SAS
Inventor： Aurelie Arnaud
CPC classification number: H01L27/0248 , H01L27/0259 , H01L27/0814
Abstract: An overvoltage protection device including: a doped substrate of a first conductivity type having a first doping level, coated with a doped epitaxial layer of the second conductivity type having a second doping level; a first doped buried region of the second conductivity type having a third doping level greater than the second level, located at the interface between the substrate and the epitaxial layer in a first portion of the device; and a second doped buried region of the first conductivity type having a fourth doping level greater than the first level, located at the interface between the substrate and the epitaxial layer in a second portion of the device.
Abstract translation: 一种过电压保护装置，包括：具有第一掺杂水平的第一导电类型的掺杂衬底，涂覆有具有第二掺杂水平的第二导电类型的掺杂外延层; 所述第二导电类型的第一掺杂掩埋区具有大于所述第二电平的第三掺杂水平，位于所述器件的第一部分中的所述衬底和所述外延层之间的界面处; 以及第一导电类型的第二掺杂掩埋区，其具有大于所述第一电平的第四掺杂水平，位于所述器件的第二部分中的所述衬底和所述外延层之间的界面处。
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公开(公告)号：US20150380925A1
公开(公告)日：2015-12-31
申请号：US14725342
申请日：2015-05-29
Applicant: STMicroelectronics (Tours) SAS
Inventor： Mathieu Rouviere , Laurent Moindron , Christian Ballon
IPC: H02H3/20 , H01L27/06 , H01L27/02 , H01L29/739 , H01L49/02 , H01L29/872 , H01L29/78
CPC classification number: H02H3/20 , H01L27/0248 , H01L27/0262 , H01L27/0629 , H01L27/0761 , H01L28/20 , H01L29/732 , H01L29/7322 , H01L29/7395 , H01L29/7827 , H01L29/87 , H01L29/872
Abstract: An integrated circuit includes a vertical Shockley diode and a first vertical transistor. The diode is formed by, from top to bottom of a semiconductor substrate, a first region of a first conductivity type, a substrate of a second conductivity type, and a second region of the first conductivity type having a third region of the second conductivity type formed therein. The vertical transistor is formed by, also from top to bottom, a portion of the second region and a fourth region of the second conductivity type. The third and fourth regions are electrically connected to each other.
Abstract translation: 集成电路包括垂直Shockley二极管和第一垂直晶体管。 二极管由半导体衬底的顶部到底部形成第一导电类型的第一区域，第二导电类型的衬底和具有第二导电类型的第三区域的第一导电类型的第二区域 在其中形成。 垂直晶体管也是从顶部到底部形成第二区域的一部分和第二导电类型的第四区域。 第三和第四区域彼此电连接。
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公开(公告)号：US20150117063A1
公开(公告)日：2015-04-30
申请号：US14525460
申请日：2014-10-28
Applicant: STMICROELECTRONICS (TOURS) SAS
Inventor： Bertrand Rivet , Greca Jean Charles , Frederic Lanois
Abstract: A circuit includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor includes a first diode with drain, source, gate and first additional electrodes. The second field-effect transistor includes a second diode with drain, source, gate and second additional electrodes. A first switch selectively connects the gate and drain electrodes of the first field-effect transistor. A second switch selectively connects the gate and drain electrodes of the second field-effect transistor. A control circuit controls the first and second switches. The first additional electrode is coupled to the gate electrode of the second field-effect transistor, and the second additional electrode is coupled to the gate electrode of the first field-effect transistor.
Abstract translation: 电路包括第一场效应晶体管和第二场效应晶体管。 第一场效应晶体管包括具有漏极，源极，栅极和第一附加电极的第一二极管。 第二场效应晶体管包括具有漏极，源极，栅极和第二附加电极的第二二极管。 第一开关选择性地连接第一场效应晶体管的栅电极和漏电极。 第二开关选择性地连接第二场效应晶体管的栅电极和漏电极。 控制电路控制第一和第二开关。 第一附加电极耦合到第二场效应晶体管的栅电极，第二附加电极耦合到第一场效应晶体管的栅电极。
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公开(公告)号：US20150023078A1
公开(公告)日：2015-01-22
申请号：US14364857
申请日：2012-11-06
Applicant: STMicroelectronics (Tours) SAS
Inventor： Benoit Renard , Laurent Gonthier
CPC classification number: H02M7/1555 , H02M7/06 , H02M7/217 , H03K17/567 , H05B39/08
Abstract: A control circuit varies the power of a load powered by an alternating voltage, comprising: a first thyristor and a first diode connected in antiparallel between first and second nodes, the cathode of the first diode being on the side of the first node; a second thyristor and a second diode connected in antiparallel between the second node and a third node, the cathode of the second diode being on the side of the third node; third and fourth diodes connected in antiseries between the first and third nodes, the cathodes of the third and fourth diodes being connected to a fourth node; a transistor between the second and fourth nodes; and a control unit for controlling the first and second thyristors and the transistor.
Abstract translation: 控制电路改变由交流电压供电的负载的功率，包括：第一晶闸管和连接在第一和第二节点之间的反平行的第一二极管，第一二极管的阴极位于第一节点的侧面; 在第二节点和第三节点之间反并联连接的第二晶闸管和第二二极管，第二二极管的阴极位于第三节点的一侧; 连接在第一和第三节点之间的反电容中的第三和第四二极管，第三和第四二极管的阴极连接到第四节点; 第二和第四节点之间的晶体管; 以及用于控制第一和第二晶闸管和晶体管的控制单元。
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公开(公告)号：US20140361747A1
公开(公告)日：2014-12-11
申请号：US14222056
申请日：2014-03-21
Applicant: STMicroelectronics (Tours) SAS
Inventor： Emilien Bouyssou , Igor Bimbaud
IPC: H02J7/00
CPC classification number: H02J7/007 , H01M6/40 , H01M6/5077 , H01M10/0436 , H01M10/052 , H01M10/0525 , H01M10/0562 , H01M10/4242 , H01M10/44 , H01M10/443 , H01M10/486 , H01M16/00 , H02J7/0075 , H02J7/34 , Y02E60/122
Abstract: A method for managing the lifetime of a battery is disclosed herein. An ambient temperature is measured near a battery. A discharge of the battery is triggered when the ambient temperature exceeds a first temperature threshold. The battery can then be charged when the ambient temperature decreases below a second temperature threshold.
Abstract translation: 本文公开了一种用于管理电池寿命的方法。 在电池附近测量环境温度。 当环境温度超过第一温度阈值时，触发电池的放电。 当环境温度降低到低于第二温度阈值时，电池可以被充电。
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Patent Agency Ranking
公开(公告)号：US08901601B2
公开(公告)日：2014-12-02
申请号：US13774554
申请日：2013-02-22
Inventor： Samuel Menard , Yannick Hague , Gaël Gautier
IPC: H01L29/74 , H01L31/111 , H01L29/06 , H01L29/747 , H01L29/66
CPC classification number: H01L29/747 , H01L24/32 , H01L29/0638 , H01L29/0649 , H01L29/0661 , H01L29/66386 , H01L2224/32014
Abstract: A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring.
Abstract translation: 一种垂直功率分量，包括第一导电类型的硅衬底，并且在支撑单个电极的下表面侧，在所述下表面侧具有第二导电类型的阱，所述第二导电类型的阱在所述下表面侧具有周边 至少部分地填充有钝化物的沟槽，以及阱和沟槽之间的多孔硅绝缘环。
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公开(公告)号：US08773217B2
公开(公告)日：2014-07-08
申请号：US13907455
申请日：2013-05-31
Applicant: STMicroelectronics (Tours) SAS
Inventor： François Dupont , Hilal Ezzeddine , Sylvain Charley
Abstract: A distributed-line directional coupler including: a first conductive line between first and second ports intended to convey a signal to be transmitted; and a second conductive line, coupled to the first one, between third and fourth ports, the second line being interrupted approximately at its middle, the two intermediary ends being connected to attenuators.
Abstract translation: 一种分布式定向耦合器，包括：用于传送待传输信号的第一和第二端口之间的第一导线; 以及在第三和第四端口之间耦合到第一端口的第二导线，第二线在其中间大致中断，两个中间端连接到衰减器。
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公开(公告)号：US20130228822A1
公开(公告)日：2013-09-05
申请号：US13774554
申请日：2013-02-22
Inventor： Samuel Menard , Yannick Hague , Gaël Gautier
IPC: H01L29/747
CPC classification number: H01L29/747 , H01L24/32 , H01L29/0638 , H01L29/0649 , H01L29/0661 , H01L29/66386 , H01L2224/32014
Abstract: A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring.
Abstract translation: 一种垂直功率分量，包括第一导电类型的硅衬底，并且在支撑单个电极的下表面侧，在所述下表面侧具有第二导电类型的阱，所述第二导电类型的阱在所述下表面侧具有周边 至少部分地填充有钝化物的沟槽，以及阱和沟槽之间的多孔硅绝缘环。
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公开(公告)号：US20240113704A1
公开(公告)日：2024-04-04
申请号：US18371622
申请日：2023-09-22
Applicant: STMicroelectronics (Tours) SAS
Inventor： Diawoye CISSE , Bertrand RIVET , Frederic GAUTIER
CPC classification number: H03K17/063 , H02M1/08 , H02M3/156
Abstract: A method for controlling a MOS transistor compares a first voltage between a drain and a source of the MOS transistor to a second controllable threshold voltage. When the first voltage is smaller than a third voltage, a fourth control voltage is applied to the MOS transistor that is greater than a fifth threshold voltage of the MOS transistor. When the first voltage is greater than the second voltage, the fourth control voltage applied to the MOS transistor is smaller than the fifth voltage. The second voltage is equal to a first constant value between a first time and a second time, and is equal to a second variable value between the second time and a third time. The second value is equal to a sum of the first voltage and a sixth positive voltage. The third time corresponds to a time when the first voltage inverts.
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公开(公告)号：US11935884B2
公开(公告)日：2024-03-19
申请号：US18060448
申请日：2022-11-30
Applicant: STMICROELECTRONICS S.r.l. , STMICROELECTRONICS (TOURS) SAS
Inventor： Jean-Michel Simonnet , Sophie Ngo , Simone Rascuna'
IPC: H01L27/02 , H01L29/04 , H01L29/16 , H01L29/20 , H01L29/417 , H01L29/868 , H02H9/04
CPC classification number: H01L27/0255 , H01L29/04 , H01L29/16 , H01L29/1608 , H01L29/2003 , H01L29/417 , H01L29/868 , H02H9/046
Abstract: Overvoltage protection circuits are provided. In some embodiments, an overvoltage protection circuit includes a first diode made of a first semiconductor material having a bandgap width greater than that of silicon. A second diode is included and is electrically cross-coupled with the first diode. The second diode is made of a second semiconductor material different from the first semiconductor material.
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