公开(公告)号：US20150311287A1

公开(公告)日：2015-10-29

申请号：US14695787

申请日：2015-04-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Fabrice NEMOUCHI ,  Emilie BOURJOT

IPC: H01L29/10 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/31051 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

Abstract: Fabrication of a field-effect transistor is performed on a substrate comprising a film made from first semiconductor material, a gate dielectric covered by a gate electrode, source and drain areas separated by the gate electrode, a protection layer covering gate electrode and source and drain areas, and an access hole to the source area and/or to drain area. Metallic material is deposited in the access hole in contact with the first semiconductor material of the source and/or drain area. An electrically conducting barrier layer that is non-reactive with the first semiconductor material and with the metallic material is deposited before reaction of metallic material with first semiconductor material. Transformation heat treatment of the metallic material with the semiconductor material is performed to form a metallic material having a base formed by the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas.

Abstract translation: 在包括由第一半导体材料制成的膜，由栅电极覆盖的栅极电介质，由栅极电极分离的源极和漏极区域的衬底，覆盖栅电极的保护层和源极和漏极的衬底上进行场效应晶体管的制造 区域，以及到源区和/或排水区的通孔。 金属材料沉积在与源极和/或漏极区域的第一半导体材料接触的入口孔中。 在金属材料与第一半导体材料反应之前，沉积与第一半导体材料和金属材料不反应的导电阻挡层。 进行具有半导体材料的金属材料的变形热处理，以形成具有由半导体材料形成的基底的金属材料，该基底在布置在源极和漏极区域之间的导电通道上产生一组应力。

公开(公告)号：US09136233B2

公开(公告)日：2015-09-15

申请号：US14293341

申请日：2014-06-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L29/06 ,  H01L21/30 ,  H01L23/00 ,  H01L23/427 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4275 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: A three-dimensional integrated structure includes a first integrated circuit having a substrate assembled in an interlocking manner with a second integrated circuit having a substrate. The substrate of the first integrated circuit comprises first pores separated by first partitions, and the substrate of the second integrated circuit comprises second pores separated by second partitions. The first partitions interlock with the second pores and the second partitions interlock with the first pores so as to define at least one region bounded by the two substrates. A phase-change material is retained within the at least one region.

Abstract translation: 三维集成结构包括具有与具有基板的第二集成电路以互锁方式组装的基板的第一集成电路。 第一集成电路的衬底包括由第一隔板分开的第一孔，并且第二集成电路的衬底包括由第二隔板分开的第二孔。 与第二孔互锁的第一隔板和第二隔板与第一孔互锁，以限定由两个基板界定的至少一个区域。 相变材料保留在至少一个区域内。

公开(公告)号：US20150253523A1

公开(公告)日：2015-09-10

申请号：US14637559

申请日：2015-03-04

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert MANOUVRIER ,  Estelle Batail

IPC: G02B6/42 ,  H01L21/768 ,  H01L49/02 ,  G02B6/13

CPC classification number: G02B6/4275 ,  G02B6/13 ,  G02F1/025 ,  G02F2202/22 ,  H01L21/768 ,  H01L27/0248 ,  H01L28/40

Abstract: An ESD protection device for an electro-optical device may include an optical waveguide segment being in semiconductor material and including a central zone of a first conductivity type, and first and second wings of a second conductivity type different from the first conductivity type and being integral with the central zone. The ESD protection device may include a first conduction terminal on the first wing for defining a first protection terminal, a second conduction terminal on the second wing for defining a second protection terminal, and a resistive contact structure of the first conductivity type having a transverse arm integral with the central zone, and an end in ohmic contact with the first conduction terminal, the resistive contact structure being electrically insulated from the first wing.

Abstract translation: 用于电光装置的ESD保护装置可以包括半导体材料中的光波导段，并且包括第一导电类型的中心区，以及不同于第一导电类型的第二导电类型的第一和第二翼， 与中央区。 ESD保护装置可以包括在第一翼上的用于限定第一保护端子的第一导电端子，用于限定第二保护端子的第二机翼上的第二导电端子，以及具有横臂的第一导电类型的电阻接触结构 与中心区域成一体，并且与第一导电端子欧姆接触的端部，电阻接触结构与第一机翼电绝缘。

公开(公告)号：US20150200099A1

公开(公告)日：2015-07-16

申请号：US14669183

申请日：2015-03-26

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： PIERRE CAUBET ,  SYLVAIN BAUDOT

IPC: H01L21/28 ,  H01L21/285

CPC classification number: H01L21/28088 ,  H01L21/28158 ,  H01L21/28556 ,  H01L29/4966

Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.

Abstract translation: 一种MOS晶体管，其具有包含高介电常数的电介质的栅极绝缘体和包含TiN层的导电层，其中TiN层中的氮组成在其下部为亚化学计量比，并且在其上部逐渐增加至化学计量组成。

公开(公告)号：US20150117128A1

公开(公告)日：2015-04-30

申请号：US14527166

申请日：2014-10-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre CAUBET ,  Mickael GROS-JEAN

IPC: G11C11/42 ,  G02F1/15 ,  H01L31/0224

CPC classification number: G11C11/42 ,  G02F1/15 ,  G02F1/1523 ,  G02F1/1525 ,  G02F1/1527 ,  G02F1/163 ,  G02F3/022 ,  G02F2001/1512 ,  G02F2001/1635 ,  G02F2201/58 ,  G11C7/00 ,  G11C13/04

Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.

Abstract translation: 存储器件可以包括存取晶体管，以及被配置为存储信息项的存储单元。 存储单元可以包括被配置为具有分别对应于信息项的两个值的不同光电子状态的第一和第二电极，以及基于存储单元外部的控制信号在不同的光电子态之间切换，不同的光电子态是 在没有控制信号的情况下自然稳定。 存储单元还可以包括在第一和第二电极之间的固体电解质。

公开(公告)号：US09018614B2

公开(公告)日：2015-04-28

申请号：US14018223

申请日：2013-09-04

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Jean-Francois Nodin ,  Veronique Sousa ,  Sandrine Lhostis

IPC: H01L47/00 ,  H01L45/00

CPC classification number: H01L45/1246 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/165 ,  H01L45/1683

Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a central region laterally surrounded with a peripheral region, the crystallization and melting temperatures of the central region being respectively lower than those of the peripheral region.

Abstract translation: 一种存储单元，包括由布置在下电极和上电极之间的相变材料制成的通孔，其中所述通孔包括横向围绕周边区域的中心区域，所述中心区域的结晶和熔融温度分别低于 那些周边地区。

公开(公告)号：US20150108576A1

公开(公告)日：2015-04-23

申请号：US14501639

申请日：2014-09-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： David BARGE ,  Philippe GARNIER ,  Yves CAMPIDELLI

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/08 ,  H01L27/12

CPC classification number: H01L21/02609 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78618

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOT substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract translation: 集成电路包括在SOT衬底的不同区域上的NMOS晶体管和PMOS晶体管。 每个晶体管包括栅极区域，在栅极区域的侧面上的多层横向绝缘区域，同时也在衬底上。 每个多层横向绝缘区域包括远离基板倾斜的倾斜部分。 源区和漏区在衬底上，并通过相应的多层横向绝缘区与栅极区的侧面分离。 源极和漏极区域具有靠在横向绝缘区域的倾斜部分的倾斜部分。

公开(公告)号：US20150093067A1

公开(公告)日：2015-04-02

申请号：US14492435

申请日：2014-09-22

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Jean-Robert MANOUVRIER ,  Frédéric BOEUF

IPC: G02F1/225

CPC classification number: G02F1/025 ,  G02F1/225 ,  G02F2001/212

Abstract: An electro-optical phase shifter to be located in an optical waveguide may include a rib of a semiconductor material extending along a length of the optical waveguide and a control structure configured to modify a concentration of carriers in the rib according to a control voltage present between first and second control terminals of the phase shifter. The control structure may include a conductive layer covering a portion of the rib and electrically connected to a first of the control terminals. An insulating layer may be configured to electrically isolate the conductive layer from the rib.

Abstract translation: 位于光波导中的电光移相器可以包括沿着光波导的长度延伸的半导体材料的肋，以及控制结构，其被配置为根据存在于所述肋之间的控制电压来修改肋中的载流子的浓度 移相器的第一和第二控制端子。 控制结构可以包括覆盖肋的一部分并电连接到第一控制端的导电层。 绝缘层可以被配置为将导电层与肋电隔离。

公开(公告)号：US08975154B2

公开(公告)日：2015-03-10

申请号：US13653911

申请日：2012-10-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Zahra Aitfqirali-Guerry ,  Yves Campidelli ,  Denis Pellissier-Tanon

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76237

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract translation: 在包括硅并且具有前侧的半导体衬底中产生至少一个深沟槽隔离的方法可以包括从前侧形成半导体衬底中的至少一个空腔。 该方法可以包括在腔的壁上共形沉积掺杂剂原子，并且在空腔的壁附近形成掺杂有掺杂剂原子的硅区。 该方法还可以包括用填充材料填充空腔以形成至少一个深沟槽隔离。

公开(公告)号：US20150054042A1

公开(公告)日：2015-02-26

申请号：US14462724

申请日：2014-08-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Sebastien Jouan ,  Laurent Frey ,  Salim Boutami

IPC: H01L27/144 ,  H01L31/101 ,  H01L29/49 ,  H01L29/66 ,  H01L29/16 ,  H01L31/18 ,  H01L31/107

CPC classification number: H01L27/1443 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/6656 ,  H01L31/02327 ,  H01L31/1016 ,  H01L31/107 ,  H01L31/1804

Abstract: A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed.

Abstract translation: 光电二极管包括布置在光电二极管半导体衬底的光接收表面上的至少一个中心衬垫。 衬垫由第一材料制成，并且包括由具有与第一材料不同的光学折射率的第二材料制成的间隔件包围的侧壁。 焊盘的横向尺寸小于光电二极管的工作波长。 第一和第二材料都对该工作波长是透明的。 焊盘和间隔物同时形成栅电极和MOS晶体管的侧壁间隔物。