公开(公告)号：US12176206B2

公开(公告)日：2024-12-24

申请号：US18332056

申请日：2023-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu Ling Liao ,  Chung-Chi Ko ,  Wan-Yi Kao

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

公开(公告)号：US12175180B2

公开(公告)日：2024-12-24

申请号：US18232742

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chung Hsu ,  Yen-Pin Chen ,  Sung-Yen Yeh ,  Jerry Chang-Jui Kao ,  Chung-Hsing Wang

IPC: G06F30/392 ,  G06F30/367 ,  G06F113/18 ,  G06F119/06

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

公开(公告)号：US12173736B2

公开(公告)日：2024-12-24

申请号：US18365776

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jheng-Syun Li ,  Mao-Chou Huang

IPC: F15D1/06 ,  C23C16/44 ,  C23C16/455 ,  C23C16/50 ,  H01J37/32 ,  H01L21/67

Abstract: A conduit system for transporting gas from a gas containing chamber for processing a substrate from which semiconductor devices are formed includes a liner with a spiral vent. The conduit system utilizes a curtain of gas to prevent or reduce deposition of material onto an inner surface of the conduit transporting the gas from the gas containing chamber.

公开(公告)号：US20240419069A1

公开(公告)日：2024-12-19

申请号：US18335852

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren ZI ,  Yen-Yu KUO ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/004 ,  G03F7/075 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/38

Abstract: A method for forming a semiconductor device is provided. The method includes forming a photoresist layer comprising an organometallic compound over a substrate. The organometallic compound includes a metal core, at least one hydrolyzable ligand bonded to the metal core, and at least one photoacid generator ligand bonded to the metal core. The method further includes selectively exposing the photoresist layer to radiation and developing the photoresist layer to form a pattern in the photoresist layer.

公开(公告)号：US12170274B2

公开(公告)日：2024-12-17

申请号：US17701083

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L27/01 ,  H01L49/02

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

公开(公告)号：US12170267B2

公开(公告)日：2024-12-17

申请号：US18300175

申请日：2023-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/52 ,  H01L23/538 ,  H01L25/065

Abstract: A structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.

公开(公告)号：US12170241B2

公开(公告)日：2024-12-17

申请号：US17837517

申请日：2022-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Feng-Wei Kuo ,  Wen-Shiang Liao

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/00 ,  H01L23/29 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L49/02

Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

公开(公告)号：US12170207B2

公开(公告)日：2024-12-17

申请号：US18447460

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

公开(公告)号：US12170203B2

公开(公告)日：2024-12-17

申请号：US17581787

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Chu-Yuan Hsu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.

公开(公告)号：US12170199B2

公开(公告)日：2024-12-17

申请号：US18362136

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Je-Ming Kuo ,  Yen-Chun Huang ,  Chih-Tang Peng ,  Tien-I Bao

IPC: H01L21/02 ,  B05D3/06 ,  B05D7/00 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  B05D1/00 ,  B05D1/38 ,  G03F7/16 ,  H01L21/768

Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.