公开(公告)号：US07442967B2

公开(公告)日：2008-10-28

申请号：US11407633

申请日：2006-04-20

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L31/0328

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

Abstract translation: 晶体管包括覆盖沟道区的栅极电介质。 源极区域和漏极区域位于沟道区域的相对侧上。 沟道区由第一半导体材料形成，源极和漏极区由第二半导体材料形成。 栅极电极覆盖栅极电介质。 在栅电极的侧壁上形成一对间隔物。 每个间隔件包括邻近通道区域的空隙。 高应力膜可以覆盖栅电极和间隔物。

公开(公告)号：US20080224227A1

公开(公告)日：2008-09-18

申请号：US11717484

申请日：2007-03-13

Applicant: Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L27/06

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

公开(公告)号：US20080224225A1

公开(公告)日：2008-09-18

申请号：US11717450

申请日：2007-03-13

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7845

Abstract: The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor.

Abstract translation: 第一和第二CMOS晶体管的通道可以选择性地受到压力。 第一晶体管的栅极结构包括在第一晶体管的沟道中产生应力的应力源。 第二晶体管的栅极结构设置成与在第二晶体管的沟道中产生应力的材料层接触。

公开(公告)号：US07418780B2

公开(公告)日：2008-09-02

申请号：US11560787

申请日：2006-11-16

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: H01K3/10 ,  H05K3/36

CPC classification number: H05K3/4652 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An exemplary method for forming stacked via-holes in a multilayer printed circuit board includes the steps of: providing a base circuit board; attaching a first copper-coated-substrate having a first substrate and a first copper layer thereon and a second copper-coated-substrate having a second substrate and a second copper layer thereon onto the base circuit board in a manner such that; forming at least one first window in the second copper layer, making at least one first hole in the second substrate through the at least one first window, forming at least one second window in the first copper layer through the at least one first hole, and making at least one second hole in the first substrate through the at least one second window, thus forming at least one part-finished stacked via-hole; and plating the at least one part-finished stacked via-hole thereby forming at least one stacked via-hole.

Abstract translation: 在多层印刷电路板中形成堆叠的通孔的示例性方法包括以下步骤：提供基底电路板; 将其上具有第一基板和第一铜层的第一铜涂覆基板和其上具有第二基板和第二铜层的第二铜涂覆基板以如下方式附接到基板电路板上; 在所述第二铜层中形成至少一个第一窗口，通过所述至少一个第一窗口在所述第二基板中形成至少一个第一孔，通过所述至少一个第一孔在所述第一铜层中形成至少一个第二窗口，以及 通过所述至少一个第二窗口在所述第一基板中形成至少一个第二孔，从而形成至少一个部分完成的堆叠通孔; 以及对所述至少一个部分精加工的堆叠通孔进行电镀，从而形成至少一个堆叠的通孔。

公开(公告)号：US20080185617A1

公开(公告)日：2008-08-07

申请号：US11702390

申请日：2007-02-05

Applicant: Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L29/78

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor structure includes a semiconductor substrate having a top surface; a gate stack on the semiconductor substrate; and a stressor in the semiconductor substrate and adjacent the gate stack. The stressor comprises at least a first portion with a first top surface lower than the top surface of the semiconductor substrate.

Abstract translation: 半导体结构包括具有顶表面的半导体衬底; 半导体衬底上的栅极堆叠; 以及半导体衬底中的紧邻栅叠层的应力器。 所述应力器至少包括具有比所述半导体衬底的顶表面低的第一顶表面的第一部分。

公开(公告)号：US20080142888A1

公开(公告)日：2008-06-19

申请号：US12040877

申请日：2008-03-01

Applicant: Chih-Hsin KO ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin KO ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L27/00

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

Abstract translation: 半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。

公开(公告)号：US20080141527A1

公开(公告)日：2008-06-19

申请号：US11861650

申请日：2007-09-26

Applicant: CHENG-HSIEN LIN ,  WEN-CHIN LEE

Inventor： CHENG-HSIEN LIN ,  WEN-CHIN LEE

IPC: H05K3/46

CPC classification number: H05K3/4611 ,  H05K1/0393 ,  H05K3/281 ,  H05K3/386 ,  H05K3/4635 ,  H05K3/4638 ,  H05K3/4652 ,  H05K3/4679 ,  H05K2201/09063 ,  H05K2203/068 ,  H05K2203/1476 ,  H05K2203/166 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: The present inventions relates to a method for manufacturing a multilayer FPCB. The method includes the steps of providing three copper clad laminates and two binder layers, each of the copper clad laminates includes a dielectric layer and at least one patterned conductive layer formed on the dielectric layer; stacking the copper clad laminates and the binder layers alternately one on another; aligning the copper clad laminates and the binder layers; and compressing the copper clad laminates and the binder layers together thereby obtaining a multilayer flexible printed circuit board.

Abstract translation: 本发明涉及一种多层FPCB的制造方法。 该方法包括以下步骤：提供三个覆铜层压板和两个粘合剂层，每个覆铜层压板包括介电层和形成在介电层上的至少一个图案化导电层; 将覆铜层压板和粘合剂层交替地堆叠在一起; 对准覆铜层压板和粘合剂层; 并且将覆铜层压板和粘合剂层压在一起，从而获得多层柔性印刷电路板。

公开(公告)号：US20080029219A1

公开(公告)日：2008-02-07

申请号：US11610642

申请日：2006-12-14

Applicant: WEN-CHIN LEE ,  CHENG-HSIEN LIN

Inventor： WEN-CHIN LEE ,  CHENG-HSIEN LIN

IPC: C23F1/00

CPC classification number: H05K3/068 ,  B05B1/205 ,  H05K2203/075 ,  Y10S134/902

Abstract: An apparatus (100) for spraying an etchant solution on a preformed printed circuit board (30) includes a number of feed pipes (40) for supplying the etchant solution and a number of nozzles (45) mounted on the feed pipes. Each of the feed pipes has a middle portion (402) and two end portions (401). The middle portions of the feed pipes are located on a first plane and the end portions of the feed pipes are located on a second plane parallel to the first plane. The number of nozzles are mounted on the middle portion and the two end portions of each feed pipe. The number of nozzles are in fluid communication with the feed pipes.

Abstract translation: 用于在预成型印刷电路板（30）上喷涂蚀刻剂溶液的装置（100）包括用于供应蚀刻剂溶液的多个进料管（40）和安装在进料管上的多个喷嘴（45）。 每个进料管具有中间部分（402）和两个端部（401）。 进料管的中间部分位于第一平面上，并且进料管的端部位于平行于第一平面的第二平面上。 喷嘴的数量安装在每个进料管的中间部分和两个端部。 喷嘴的数量与进料管流体连通。

公开(公告)号：US20070117358A1

公开(公告)日：2007-05-24

申请号：US11622490

申请日：2007-01-12

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: H01L27/12 ,  H01L21/20

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US20070093046A1

公开(公告)日：2007-04-26

申请号：US11562522

申请日：2006-11-22

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: H01L21/3205

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L29/78

Abstract: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.

Abstract translation: 公开了一种制造微电子器件的方法，包括用具有不同掺杂剂特性的第一和第二阱形成硅衬底，形成靠近第一阱的第一制剂的第一应变硅 - 锗 - 碳层，以及形成第二应变硅 - 不同于靠近第二孔的第一制剂的第二制剂的锗 - 碳层。 然后形成封盖和绝缘层，栅极结构，间隔物以及源极和漏极，从而产生具有独立应变通道的CMOS器件。