公开(公告)号：US10319833B1

公开(公告)日：2019-06-11

申请号：US15831340

申请日：2017-12-04

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Choonghyun Lee ,  Alexander Reznicek ,  Christopher Waskiewicz

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.

公开(公告)号：US10319826B2

公开(公告)日：2019-06-11

申请号：US15485727

申请日：2017-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee

IPC: H01L21/70 ,  H01L29/49 ,  H01L29/66 ,  H01L21/285 ,  H01L21/28 ,  H01L29/78

Abstract: A method is presented for tuning work functions of transistors. The method includes forming a high-k dielectric over a semiconductor substrate, and forming a work function stack over the high-k dielectric, the work function stack including a first layer having a nitrogen (N) scavenging element, a second layer having an oxygen (O) scavenging element, and a third layer being a conducting layer.

公开(公告)号：US10319643B1

公开(公告)日：2019-06-11

申请号：US15890699

申请日：2018-02-07

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L21/308 ,  H01L29/78 ,  H01L21/3065

Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes depositing a strain relaxed buffer (SRB) layer over a substrate; recessing the SRB layer on a first region of the structure; and forming a first semiconductor layer on the first region of the structure and depositing one or more mandrels over the first semiconductor layer of the first region of the structure. The method further includes depositing a spacer layer over the one or more mandrels, the spacer layer including vertical portions and horizontal portions; and removing the one or more mandrels and the horizontal portions of the spacer layer. The method further includes performing a reactive ion etch to remove material unprotected by the spacer to form a first channel for a p-type vertical field effect transistor from the first semiconductor layer. The first channel has a compressive strain.

公开(公告)号：US20190172922A1

公开(公告)日：2019-06-06

申请号：US16215027

申请日：2018-12-10

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Takashi Ando ,  Jingyun Zhang ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3215 ,  H01L21/28 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

公开(公告)号：US20190157424A1

公开(公告)日：2019-05-23

申请号：US16144141

申请日：2018-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238

Abstract: Semiconductor devices include a semiconductor layer comprising a channel region and source/drain regions. A gate stack is formed on the channel region. A dielectric layer is formed on the semiconductor layer in the source/drain regions. Source/drain structures are formed over the dielectric layer in the source/drain regions.

公开(公告)号：US10283565B1

公开(公告)日：2019-05-07

申请号：US15850400

申请日：2017-12-21

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee

IPC: H01L21/301 ,  H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L21/768 ,  H01L29/78 ,  H01L27/115

Abstract: A method of forming a semiconductor structure includes forming a plurality of vertical field-effect transistors (VFETs) disposed on a substrate and forming a plurality of resistive elements disposed over top surfaces of the VFETs. Each pair of a given one of the plurality of VFETs and a corresponding resistive element disposed over the given VFET provides a resistive random access memory (ReRAM) cell. The VFETs are arranged in two or more columns and two or more rows, wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region and wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate. Top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs.

公开(公告)号：US20190131396A1

公开(公告)日：2019-05-02

申请号：US15802067

申请日：2017-11-02

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78651 ,  H01L29/78684

Abstract: A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET S/D structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.

公开(公告)号：US20190123174A1

公开(公告)日：2019-04-25

申请号：US15791095

申请日：2017-10-23

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Michael P. Belyansky ,  Choonghyun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831 ,  H01L2029/7858

Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

公开(公告)号：US10170577B1

公开(公告)日：2019-01-01

申请号：US15830963

申请日：2017-12-04

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Takashi Ando ,  Jingyun Zhang ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/00 ,  H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

公开(公告)号：US20180374917A1

公开(公告)日：2018-12-27

申请号：US16117754

申请日：2018-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee

IPC: H01L29/06

CPC classification number: H01L29/0607 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/324 ,  H01L21/82345 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517

Abstract: A method is presented for tuning work functions of transistors. The method includes forming a work function stack over a semiconductor substrate, depositing a germanium oxide layer and a barrier layer over the work function stack, and annealing the germanium oxide layer to desorb oxygen therefrom to trigger oxidation of at least one conducting layer of the work function stack. The work function stack includes three layers, that is, a first layer being a TiN layer, a second layer being a titanium aluminum carbon (TiAlC) layer, and a third layer being a second TiN layer.