公开(公告)号：US09093142B2

公开(公告)日：2015-07-28

申请号：US14171239

申请日：2014-02-03

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

Abstract: Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated.

Abstract translation: 一些实施例包括具有模块的方法和装置，其被配置为使用信号对存储器单元进行编程以使存储器单元具有编程的电阻值，以便如果编程的电阻值在目标电阻值之外，则调整该信号的编程参数值 并且如果编程的电阻值在目标电阻值范围之外，则重复编程和调整中的至少一个，该信号在每次重复编程时包括不同的编程参数值。

公开(公告)号：US20150078073A1

公开(公告)日：2015-03-19

申请号：US14553758

申请日：2014-11-25

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

Abstract translation: 配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。 这些装置包括具有两个钉扎层和其间的自由层的存储单元。 通过利用两个固定层，分别从两个固定层中的每一个自由层上的自旋转矩效应允许以单向电流编程存储器单元。

公开(公告)号：US20150041753A1

公开(公告)日：2015-02-12

申请号：US14524322

申请日：2014-10-27

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal R. Parekh

IPC: H01L45/00

CPC classification number: H01L45/16 ,  H01L21/0337 ,  H01L21/76807 ,  H01L21/76816 ,  H01L27/2472 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalk of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of as first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

Abstract translation: 可以通过沿电介质结构的人行道形成电介质衬垫来形成电接触件，沿着牺牲结构的侧壁在电介质衬垫之上和横向于形成牺牲衬垫，在电介质衬垫和牺牲衬套的交叉处选择性地去除部分电介质衬垫到 形成孔，并且用导电材料至少部分地填充孔。 可以通过类似的方法形成纳米尺度的孔。 可以形成底部电极，并且电触点可以在结构上和电耦合到底部电极以形成存储器件。 纳米级电触头可以具有作为第一宽度和第二宽度的矩形横截面，每个宽度小于约20nm。 存储器件可以包括底部电极，具有小于约150nm 2的横截面积并且电耦合到底部电极的电触点，以及电触点上的电池材料。

公开(公告)号：US08917542B2

公开(公告)日：2014-12-23

申请号：US13746206

申请日：2013-01-21

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: G11C11/02 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L43/02

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

Abstract translation: 配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。 这些装置包括具有两个钉扎层和其间的自由层的存储单元。 通过利用两个固定层，分别从两个固定层中的每一个自由层上的自旋转矩效应允许以单向电流编程存储器单元。

公开(公告)号：US20140220763A1

公开(公告)日：2014-08-07

申请号：US14247653

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: H01L45/00 ,  H01L21/02

CPC classification number: H01L21/02225 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.

Abstract translation: 一种方法包括在具有含金属的导电互连的集成电路上形成电绝缘体材料，并激活衬底的半导体材料中的掺杂剂以提供掺杂区域。 掺杂区域提供相反导电类型的结。 在激活掺杂剂之后，衬底被结合到绝缘体材料上，并且至少部分衬底在与绝缘体材料接合的情况下被去除。 在移除之后，形成具有字线，存取二极管，含有硫族化物相变材料的状态可变存储元件和全部电连接的位线的存储单元，该存储二极管包含该结作为pn结 。 存储器件包括绝缘体材料上的粘合材料并将字线连接到绝缘体材料上。

公开(公告)号：US20140154860A1

公开(公告)日：2014-06-05

申请号：US14173096

申请日：2014-02-05

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: H01L45/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/165

Abstract: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another.

Abstract translation: 一些实施例包括其中存储单元形成为在第一和第二访问线之间具有可编程材料的方法，其中可编程材料具有两个组成上不同的区域。 可以在至少一个区域中改变离子和/或离子空位的浓度以改变存储器单元的存储状态并同时形成pn二极管。 一些实施例包括具有两个组成不同区域的可编程材料并且具有可扩散到至少一个区域中的离子和/或离子空位的存储器单元。 存储单元具有其中第一和第二区域相对于彼此具有相反导电类型的存储状态。

公开(公告)号：US08742386B2

公开(公告)日：2014-06-03

申请号：US13903307

申请日：2013-05-28

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: H01L29/04

CPC classification number: H01L45/145 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1683

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide.

Abstract translation: 与基于氧化物的存储器相关联的方法，装置和系统可以包括形成基于氧化物的存储器单元的方法。 形成基于氧化物的存储单元可以包括形成第一导电元件，在第一导电元件上形成亚化学计量氧化物，在亚化学计量氧化物上形成第二导电元件，以及通过使亚化学计量氧化物氧化成氧化环境来氧化亚化学计量氧化物的边缘 以限定氧化物中心附近的受控氧空位传导路径。

公开(公告)号：US20140138604A1

公开(公告)日：2014-05-22

申请号：US13683418

申请日：2012-11-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

Abstract translation: 在一些实施例中，集成电路包括填充集成电路中形成的开口的窄的垂直延伸柱。 在一些实施例中，开口可以包含相变材料以形成相变存储器单元。 支柱所占据的开口可以使用在不同垂直水平上形成的牺牲材料（例如间隔物）的交叉线来限定。 材料线可以通过允许形成非常细线的沉积工艺形成。 选择性地去除在线交叉点处的暴露材料以形成具有由线的宽度确定的尺寸的开口。 开口可以例如用相变材料填充。

公开(公告)号：US20140103288A1

公开(公告)日：2014-04-17

申请号：US14136093

申请日：2013-12-20

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: H01L45/00

CPC classification number: H01L45/141 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0023 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/1691

Abstract: Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact lines are generally parallel to each other. The memory array also includes a memory node that includes a first memory cell electrically connected between the access line and the first contact line to form a first circuit, and a second memory cell electrically connected between the access line and the second contact line to form a second circuit different from the first circuit.

Abstract translation: 本文公开了存储器阵列和相关的制造方法。 在一个实施例中，存储器阵列包括沿着第一方向延伸的访问线和沿着不同于第一方向的第二方向延伸的第一接触线和第二接触线。 第一和第二接触线通常彼此平行。 存储器阵列还包括存储器节点，其包括电连接在接入线路和第一接触线路之间以形成第一电路的第一存储器单元，以及电连接在接入线路和第二接触线路之间的第二存储器单元， 第二电路不同于第一电路。

公开(公告)号：US08681531B2

公开(公告)日：2014-03-25

申请号：US13919677

申请日：2013-06-17

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/165

Abstract: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another.

Abstract translation: 一些实施例包括其中存储单元形成为在第一和第二访问线之间具有可编程材料的方法，其中可编程材料具有两个组成上不同的区域。 可以在至少一个区域中改变离子和/或离子空位的浓度以改变存储器单元的存储状态并同时形成pn二极管。 一些实施例包括具有两个组成不同区域的可编程材料并且具有可扩散到至少一个区域中的离子和/或离子空位的存储器单元。 存储单元具有其中第一和第二区域相对于彼此具有相反导电类型的存储状态。