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    Non-volatile split gate memory device and a method of operating same
    181.
    发明授权
    Non-volatile split gate memory device and a method of operating same 有权

    公开(公告)号：US09922715B2

    公开(公告)日：2018-03-20

    申请号：US14506433

    申请日：2014-10-03

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    IPC: G11C16/14 ,  G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/12 ,  G11C16/10

    CPC classification number: G11C16/24 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

    Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

    Flash Memory System Using Complementary Voltage Supplies
    186.
    发明申请
    Flash Memory System Using Complementary Voltage Supplies 审中-公开
    使用互补电压源的闪存系统

    公开(公告)号：US20170076809A1

    公开(公告)日：2017-03-16

    申请号：US15361473

    申请日：2016-11-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/30 ,  H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

    CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C8/08 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/04 ,  H01L27/11521

    Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

    Abstract translation: 非易失性存储器件包括第一导电类型的半导体衬底。 非易失性存储单元的阵列位于半导体衬底中并且被布置成多个行和列。 每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。 沟道区域在第一区域和第二区域之间。 字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。 耦合栅极覆盖浮栅。 位线连接到第一区域。 在程序，读取或擦除的操作期间，负电压可以被施加到所选择的或未选择的存储单元的字线和/或耦合门。

    High Density Split-Gate Memory Cell
    188.
    发明申请
    High Density Split-Gate Memory Cell 审中-公开
    高密度分离栅极存储单元

    公开(公告)号：US20160217849A1

    公开(公告)日：2016-07-28

    申请号：US15002302

    申请日：2016-01-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Xian Liu ,  Vipin Tiwari ,  Hieu Van Tran

    IPC: G11C11/419 ,  G11C16/14 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788

    CPC classification number: G11C11/419 ,  G11C16/0458 ,  G11C16/14 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

    Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

    Abstract translation: 一种形成存储器件的方法，包括在衬底上形成第一绝缘层，第一导电层，第二绝缘层，第二导电层，第三绝缘层。 第一沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成，从而使第一导电层的侧面部分露出。 第一绝缘层形成在沿第一导电层的暴露部分延伸的第一沟槽的底部。 第一个沟槽填充有导电材料。 第二沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成。 在第二沟槽下的衬底中形成漏区。 导致一对存储单元，其中单个连续沟道区域在用于该对存储单元的漏极区域之间延伸。

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