公开(公告)号：USD668624S1

公开(公告)日：2012-10-09

申请号：US29406971

申请日：2011-11-21

Applicant: Bo-Yu Ko

Designer： Bo-Yu Ko

公开(公告)号：USD668623S1

公开(公告)日：2012-10-09

申请号：US29406960

申请日：2011-11-21

Applicant: Hui-Kai Hsu

Designer： Hui-Kai Hsu

公开(公告)号：US08278681B2

公开(公告)日：2012-10-02

申请号：US12469669

申请日：2009-05-20

Applicant: Chia-En Lee ,  Cheng-Ta Kuo ,  Der-Ling Hsia

Inventor： Chia-En Lee ,  Cheng-Ta Kuo ,  Der-Ling Hsia

IPC: H01L33/00

CPC classification number: H01L33/0079 ,  H01L24/26 ,  H01L24/93 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/00

Abstract: A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.

Abstract translation: 提供了发光二极管的晶片级封装工艺。 首先，在生长基板上形成半导体堆叠层。 然后在半导体堆叠层上形成多个阻挡图案和多个反射层，其中每个反射层被一个屏障图案包围。 然后在半导体堆叠层上形成第一结合层以覆盖阻挡图案和反射层。 此后，设置具有多个第二接合层和彼此电绝缘的多个导电插塞的承载基板，并且第一接合层与第二接合层接合。 然后将半导体堆叠层与生长衬底分离。 接下来，对半导体堆叠层进行图案化以形成多个半导体堆叠图案。 接下来，每个半导体堆叠图案电连接到导电插头。

公开(公告)号：US08253160B2

公开(公告)日：2012-08-28

申请号：US13050677

申请日：2011-03-17

Applicant: Jun-Rong Chen ,  Chi-Wen Kuo ,  Kun-Fu Huang ,  Jui-Yi Chu ,  Kuo-Lung Fang

Inventor： Jun-Rong Chen ,  Chi-Wen Kuo ,  Kun-Fu Huang ,  Jui-Yi Chu ,  Kuo-Lung Fang

IPC: H01L33/20

CPC classification number: H01L33/20 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/382 ,  H01L33/387

Abstract: A light-emitting diode chip structure including a conductive substrate, a semiconductor stacking layer and a patterned seed crystal layer is provided. The conductive substrate has a surface. The surface has a first region and a second region alternately distributed over the surface. The semiconductor stacking layer is disposed on the conductive substrate, and the surface of the conductive substrate faces the semiconductor stacking layer. The patterned seed crystal layer is disposed on the first region of the surface of the conductive substrate and between the conductive substrate and the semiconductor stacking layer. The patterned seed crystal layer separates the semiconductor stacking layer from the first region. The semiconductor stacking layer covers the patterned seed crystal layer and the second region, and is electrically connected to the conductive substrate through the second region. A fabrication method of the light-emitting diode chip structure is also provided.

Abstract translation: 提供了包括导电基板，半导体堆叠层和图案化晶种层的发光二极管芯片结构。 导电基板具有表面。 表面具有交替地分布在表面上的第一区域和第二区域。 半导体层叠层设置在导电性基板上，导电性基板的表面面向半导体层叠层。 图案化晶种层设置在导电基板的表面的第一区域上，并且在导电基板和半导体堆叠层之间。 图案化晶种层将半导体层叠层与第一区域分开。 半导体堆叠层覆盖图案化晶种层和第二区域，并且通过第二区域电连接到导电基板。 还提供了发光二极管芯片结构的制造方法。

公开(公告)号：US20120195049A1

公开(公告)日：2012-08-02

申请号：US13346545

申请日：2012-01-09

Applicant: Shih-Chin CHOU ,  Chun-Ming LAI ,  He-Shun YANG

Inventor： Shih-Chin CHOU ,  Chun-Ming LAI ,  He-Shun YANG

IPC: F21V29/00 ,  F21V5/04

CPC classification number: F21K9/27 ,  F21V3/04 ,  F21Y2103/10 ,  F21Y2115/10

Abstract: A lamp module is provided, including an insulative member, a cover lens connected to the insulative member, and a light module disposed between the insulative member and the cover lens. The light module can emit light through the cover lens for illumination.

Abstract translation: 提供一种灯模块，包括绝缘构件，连接到绝缘构件的盖透镜以及设置在绝缘构件和盖透镜之间的光模块。 光模块可以通过盖子透镜发光以进行照明。

公开(公告)号：USD664109S1

公开(公告)日：2012-07-24

申请号：US29402484

申请日：2011-09-23

Applicant: Chi-Kuon Wang

Designer： Chi-Kuon Wang

公开(公告)号：US20120164768A1

公开(公告)日：2012-06-28

申请号：US13403714

申请日：2012-02-23

Applicant: Chia-En Lee ,  Cheng-Ta Kuo ,  Der-Ling Hsia

Inventor： Chia-En Lee ,  Cheng-Ta Kuo ,  Der-Ling Hsia

IPC: H01L33/60

CPC classification number: H01L33/0079 ,  H01L24/26 ,  H01L24/93 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/00

Abstract: A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.

Abstract translation: 提供了发光二极管的晶片级封装工艺。 首先，在生长基板上形成半导体堆叠层。 然后在半导体堆叠层上形成多个阻挡图案和多个反射层，其中每个反射层被一个屏障图案包围。 然后在半导体堆叠层上形成第一结合层以覆盖阻挡图案和反射层。 此后，设置具有多个第二接合层和彼此电绝缘的多个导电插塞的承载基板，并且第一接合层与第二接合层接合。 然后将半导体堆叠层与生长衬底分离。 接下来，对半导体堆叠层进行图案化以形成多个半导体堆叠图案。 接下来，每个半导体堆叠图案电连接到导电插头。

公开(公告)号：US20120120668A1

公开(公告)日：2012-05-17

申请号：US13356317

申请日：2012-01-23

Applicant: Wen-Lung SU ,  Hsiang-Cheng HSIEH

Inventor： Wen-Lung SU ,  Hsiang-Cheng HSIEH

IPC: F21V15/01

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/642 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/01322 ,  H01L2924/00014

Abstract: A light emitting diode includes a casing, a frame in the casing, one or a plurality of light emitting chip, and a packaging polymer; the frame being provided 5 with a placement area to receive placement of the light emitting chip, and an electrode area separated from the placement area; a sectional fall being disposed at where appropriately on the placement area to increase contact area between the frame and the casing and improve the relative stability between the casing and the frame.

Abstract translation: 发光二极管包括壳体，壳体中的框架，一个或多个发光芯片和包装聚合物; 该框架5设置有用于接收发光芯片的放置的放置区域和与放置区域分离的电极区域; 在适当地设置在放置区域上的截面下降以增加框架和壳体之间的接触面积，并提高壳体与框架之间的相对稳定性。

公开(公告)号：US08125136B2

公开(公告)日：2012-02-28

申请号：US11656005

申请日：2007-01-22

Applicant: Wen-Lung Su ,  Hsiang-Cheng Hsieh

Inventor： Wen-Lung Su ,  Hsiang-Cheng Hsieh

IPC: H01L51/00

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/642 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/01322 ,  H01L2924/00014

Abstract: A light emitting diode includes a casing, a frame in the casing, one or a plurality of light emitting chip, and a packaging polymer; the frame being provided with a placement area to receive placement of the light emitting chip, and an electrode area separated from the placement area; a sectional fall being disposed at where appropriately on the placement area to increase contact area between the frame and the casing and improve the relative stability between the casing and the frame.

Abstract translation: 发光二极管包括壳体，壳体中的框架，一个或多个发光芯片和包装聚合物; 所述框架设置有用于接收所述发光芯片的放置的放置区域以及与所述放置区域分离的电极区域; 在适当地设置在放置区域上的截面下降以增加框架和壳体之间的接触面积，并提高壳体与框架之间的相对稳定性。

公开(公告)号：USD653223S1

公开(公告)日：2012-01-31

申请号：US29396472

申请日：2011-06-30

Applicant: Kun-Jung Wu

Designer： Kun-Jung Wu