公开(公告)号：US20110139314A1

公开(公告)日：2011-06-16

申请号：US12776607

申请日：2010-05-10

Applicant: Cheng-En Ho ,  Chi-Ming Lin

Inventor： Cheng-En Ho ,  Chi-Ming Lin

IPC: B23K31/02 ,  B23K1/20

CPC classification number: B23K1/20 ,  B23K1/0016 ,  B23K1/008 ,  B23K2101/42 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2924/14 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for inhibiting the growth of a nickel-copper-tin intermetallic (i.e. (Ni,Cu)3Sn4) layer at the (Cu,Ni)6Sn5/nickel interface of a solder joint is described as follows. A Sn—Ag—Cu solder alloy with a Cu-content of 0.5˜1 weight percent (wt. %) is provided. The solder alloy is disposed on a surface finish of a soldering pad, having a nickel-based metallization layer. A material of the solder alloy further includes palladium. The solder alloy is joined with the surface finish, so as to form the solder joint containing palladium that enables to inhibit the growth of the undesired (Ni,Cu)3Sn4 layer between the (Cu,Ni)6Sn5 and nickel in the subsequent use at temperatures ranging from 100° C. to 180° C.

Abstract translation: 焊接接头的（Cu，Ni）6Sn5 /镍界面处的镍 - 铜 - 锡 - 金属间化合物（即（Ni，Cu）3Sn4）层的生长抑制方法如下所述。 提供Cu含量为0.5〜1重量％（重量％）的Sn-Ag-Cu焊料合金。 焊料合金设置在具有镍基金属化层的焊盘的表面光洁度上。 焊料合金的材料还包括钯。 焊料合金与表面光洁度相结合，以形成含钯的焊点，其能够抑制（Cu，Ni）6 Sn 5和镍之间不期望的（Ni，Cu）3 Sn 4层在随后的使用中的生长 温度范围从100°C到180°C

公开(公告)号：US20100127047A1

公开(公告)日：2010-05-27

申请号：US12352979

申请日：2009-01-13

Applicant: Cheng-En Ho ,  Wei-Hsiang Wu ,  Cheng-Shiuan Lin

Inventor： Cheng-En Ho ,  Wei-Hsiang Wu ,  Cheng-Shiuan Lin

IPC: B23K31/02

CPC classification number: B23K1/20 ,  B23K35/262 ,  B23K35/268 ,  B23K35/40 ,  H05K3/244 ,  H05K3/3463

Abstract: A method of inhibiting a formation of palladium-nickel-tin (Pd—Ni—Sn) intermetallic in solder joints is described as follows. Firstly, a solder alloy is provided. Then, at least one of a trace of copper and a trace of zinc is doped into the solder alloy. Afterward, the solder alloy is disposed on the Pd-bearing surface finish, such as a Pd/Ni bi-layer or a Au/Pd/Ni tri-layer. Next, the solder alloy is soldered with the surface finish as solder joints. During the soldering, the Cu and Zn will incorporate into the soldering reaction, forming copper-palladium-nickel-tin intermetallic and zinc-palladium-nickel-tin intermetallic, replacing the Pd—Ni—Sn respectively. Consequently, the addition of Cu and/or Zn into solders will inhibit the undesirable Pd—Ni—Sn intermetallic to form in the solder joints.

Abstract translation: 描述了在焊接接头中抑制钯 - 镍 - 锡（Pd-Ni-Sn）金属间化合物形成的方法。 首先，提供焊料合金。 然后，将铜和痕量锌中的至少一种掺杂到焊料合金中。 之后，将焊料合金设置在Pd载体表面光洁度上，例如Pd / Ni双层或Au / Pd / Ni三层。 接下来，焊接合金以表面光洁度焊接作为焊点。 在焊接过程中，Cu和Zn将引入焊接反应，形成铜 - 钯 - 镍 - 锡金属间化合物和锌 - 钯 - 镍 - 锡金属间化合物，分别代替Pd-Ni-Sn。 因此，将Cu和/或Zn添加到焊料中将抑制在焊点中形成不期望的Pd-Ni-Sn金属间化合物。

公开(公告)号：US20090294409A1

公开(公告)日：2009-12-03

申请号：US12156560

申请日：2008-06-02

Applicant: Cheng-En Ho ,  Wei-Hsiang Wu

Inventor： Cheng-En Ho ,  Wei-Hsiang Wu

IPC: B23K11/00

CPC classification number: B23K1/0016 ,  H05K3/3436 ,  H05K2201/0769 ,  H05K2203/105 ,  H05K2203/1492 ,  Y02P70/613

Abstract: A method for inhibiting electromigration-induced phase segregation suitable for solder joint configurations used in a chip package is described as following. First, a chip package including a wiring board, a chip and numbers of solder joints is provided, wherein the chip is disposed on the wiring board, and the solder joints are disposed between the chip and the wiring board to electrically connect the chip to the wiring board. Next, a first current and a second current are alternately applied to a side of the solder joints, wherein flowing directions of the first current and the second current are opposite. The current density of the first current is 103˜105 A/cm2, and the current density of the second current is 103˜105 A/cm2.

Abstract translation: 下面描述一种用于抑制适用于芯片封装中使用的焊点配置的电迁移诱导相分离的方法。 首先，提供包括布线板，芯片和焊点数量的芯片封装，其中芯片设置在布线板上，并且焊点设置在芯片和布线板之间，以将芯片电连接到 接线板 接下来，第一电流和第二电流交替地施加到焊点的一侧，其中第一电流和第二电流的流动方向相反。 第一电流的电流密度为103〜105A / cm2，第二电流的电流密度为103〜105A / cm2。

公开(公告)号：US20080280785A1

公开(公告)日：2008-11-13

申请号：US12110551

申请日：2008-04-28

Applicant: Fan Gang Tseng ,  Cheng En Ho

Inventor： Fan Gang Tseng ,  Cheng En Ho

IPC: C40B60/14

CPC classification number: C40B60/14 ,  B01J19/0046 ,  B01J2219/0036 ,  B01J2219/00369 ,  B01J2219/00382 ,  B01J2219/00527 ,  B01J2219/00585 ,  B01J2219/00596 ,  B01L3/0255 ,  B01L3/0258 ,  B01L3/0262 ,  B01L3/563 ,  B01L2200/021 ,  B01L2200/0642 ,  B01L2300/0819 ,  B01L2400/0406

Abstract: A fluidic nano/micro array chipset comprises a microarray filling chip and a nano/micro array stamping chip. There are a plurality of sample containers and a plurality of nano/micro channels on the top of the microarray filling chip, and a plurality of nano/micro-scaled micro filling holes on the bottom of the microarray filling chip. Each nano/micro channel is connected to one of the sample containers and leads the sample solution in that sample container to the corresponding micro filling hole. The nano/micro array stamp chip comprises a plurality of stamping heads arranged in an array pattern, with a body part of the stamp chip and a plurality of space channels forming hydrophobic areas. Each sample solution is stored in the body of the stamp chip, and is transported by the corresponding stamping head to the stamping part of this stamping head.

Abstract translation: 流体纳米/微阵列芯片组包括微阵列填充芯片和纳米/微阵列冲压芯片。 在微阵列填充芯片的顶部有多个样品容器和多个纳米/微通道，以及位于微阵列填充芯片底部的多个纳米/微尺度微量填充孔。 每个纳米/微通道连接到一个样品容器中，并将样品容器中的样品溶液引导到相应的微孔中。 纳米/微阵列印模芯片包括以阵列图案排列的多个冲压头，印模芯片的主体部分和形成疏水区域的多个空间通道。 每个样品溶液储存在印模芯片的主体中，并通过相应的冲压头传送到冲压头的冲压件。