公开(公告)号：US20070215983A1

公开(公告)日：2007-09-20

申请号：US11723065

申请日：2007-03-16

Applicant: Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

Inventor： Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

IPC: H01L29/12

CPC classification number: H01L29/2003 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02664 ,  H01L33/0075

Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 μm. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.

Abstract translation: 氮化物半导体单晶衬底，其制造方法和使用其的垂直氮化物半导体器件的制造方法。 根据本发明的一个方面，在氮化物半导体单晶衬底中，沿厚度方向分割上下区域，氮化物单晶衬底的厚度至少为100μm。 这里，上部区域的掺杂浓度为下部区域的5倍以上。 优选地，上部区域中的基板的顶表面具有Ga极性。 此外，根据本发明的具体实施例，下部区域有意地未掺杂，并且上部区域是n掺杂的。 优选地，上部区域和下部区域中的每一个具有在厚度方向上基本相同的掺杂浓度。

公开(公告)号：US08017929B2

公开(公告)日：2011-09-13

申请号：US12285449

申请日：2008-10-06

Applicant: Youn-seon Kang ,  Daniel Wamwangi ,  Matthias Wuttig ,  Ki-joon Kim ,  Yoon-ho Khang ,  Cheol-kyu Kim ,  Dong-seok Suh ,  Tae-yon Lee

Inventor： Youn-seon Kang ,  Daniel Wamwangi ,  Matthias Wuttig ,  Ki-joon Kim ,  Yoon-ho Khang ,  Cheol-kyu Kim ,  Dong-seok Suh ,  Tae-yon Lee

IPC: H01L29/02

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1625

Abstract: A phase change material layer includes antimony (Sb) and at least one of indium (In) and gallium (Ga). A phase change memory device includes a storage node including a phase change material layer and a switching device connected to the storage node. The phase change material layer includes Sb and at least one of In and Ga.

Abstract translation: 相变材料层包括锑（Sb）和铟（In）和镓（Ga）中的至少一种。 相变存储器件包括：存储节点，包括相变材料层和连接到存储节点的开关器件。 相变材料层包括Sb和In和Ga中的至少一种。

公开(公告)号：US08003970B2

公开(公告)日：2011-08-23

申请号：US12073499

申请日：2008-03-06

Applicant: Cheol-kyu Kim ,  Yoon-ho Khang ,  Tae-yon Lee

Inventor： Cheol-kyu Kim ,  Yoon-ho Khang ,  Tae-yon Lee

IPC: H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided is a phase-change random access memory (PRAM). The PRAM includes a bottom electrode, a bottom electrode contact layer, which is formed on one area of the bottom electrode, and an insulating layer, which is formed on a side of the bottom electrode contact layer, a phase-change layer, which is formed on the bottom electrode contact layer and the insulating layer and is formed of a phase-change material having a crystallization temperature between 100° C. and 150° C., and a top electrode, which is formed on the phase-change layer.

Abstract translation: 提供了相变随机存取存储器（PRAM）。 PRAM包括底电极，底电极接触层，其形成在底电极的一个区域上，绝缘层形成在底电极接触层的一侧，相变层 形成在底部电极接触层和绝缘层上，并且由结晶温度在100℃至150℃之间的相变材料和形成在相变层上的顶部电极形成。

公开(公告)号：US20060148186A1

公开(公告)日：2006-07-06

申请号：US11220020

申请日：2005-09-06

Applicant: Soo Min Lee ,  Masayoshi Koike ,  Kyeong Ik Min ,  Cheol Kyu Kim ,  Sung Hwan Jang ,  Min Ho Kim

Inventor： Soo Min Lee ,  Masayoshi Koike ,  Kyeong Ik Min ,  Cheol Kyu Kim ,  Sung Hwan Jang ,  Min Ho Kim

IPC: H01L21/336

CPC classification number: C30B29/406 ,  C30B29/64 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02664

Abstract: A method and apparatus for manufacturing a nitride based single crystal substrate. The method includes placing a preliminary substrate on a susceptor installed in a reaction chamber; growing a nitride single crystal layer on the preliminary substrate; and irradiating a laser beam to separate the nitride single crystal layer from the preliminary substrate under the condition that the preliminary substrate is placed in the reaction chamber.

Abstract translation: 一种用于制造氮化物基单晶衬底的方法和装置。 该方法包括将初步衬底放置在安装在反应室中的基座上; 在初始衬底上生长氮化物单晶层; 并且在预备衬底放置在反应室中的条件下照射激光束以将氮化物单晶层与预备衬底分离。

公开(公告)号：US09252226B2

公开(公告)日：2016-02-02

申请号：US13367061

申请日：2012-02-06

Applicant: Do-Hyun Kim ,  Yoon Ho Khang ,  Dong-Hoon Lee ,  Sang Ho Park ,  Se Hwan Yu ,  Cheol Kyu Kim ,  Yong-Su Lee ,  Sung Haeng Cho ,  Chong Sup Chang ,  Dong Jo Kim ,  Jung Kyu Lee

Inventor： Do-Hyun Kim ,  Yoon Ho Khang ,  Dong-Hoon Lee ,  Sang Ho Park ,  Se Hwan Yu ,  Cheol Kyu Kim ,  Yong-Su Lee ,  Sung Haeng Cho ,  Chong Sup Chang ,  Dong Jo Kim ,  Jung Kyu Lee

IPC: H01L29/786 ,  H01L29/45 ,  H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/7869

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract translation: 提供了一种薄膜晶体管阵列面板。 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：设置在基板上的栅极布线层; 设置在所述栅极布线层上的氧化物半导体层; 以及数据布线层，其设置在所述氧化物半导体层上，所述数据布线层包括包含铜的主布线层和设置在所述主布线层上并包括铜合金的覆盖层。

公开(公告)号：US09025118B2

公开(公告)日：2015-05-05

申请号：US13619120

申请日：2012-09-14

Applicant: Jung-Kyu Lee ,  Yoon-Ho Khang ,  Se-Hwan Yu ,  Cheol-Kyu Kim ,  Yong-Su Lee ,  Chong-Sup Chang ,  Sang-Ho Park ,  Su-Hyoung Kang ,  Hyun-Jae Na ,  Young-Ki Shin

Inventor： Jung-Kyu Lee ,  Yoon-Ho Khang ,  Se-Hwan Yu ,  Cheol-Kyu Kim ,  Yong-Su Lee ,  Chong-Sup Chang ,  Sang-Ho Park ,  Su-Hyoung Kang ,  Hyun-Jae Na ,  Young-Ki Shin

IPC: G02F1/136 ,  H01L27/12 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/1288

Abstract: A display substrate includes a base substrate, a switching element, a gate line, a data line and a pixel electrode. Each of the gate line and the data line includes a first metal layer, and a second metal layer directly on the first metal layer. The switching element is on the base substrate, and includes a control electrode and an input electrode or an output electrode. The control electrode includes the first metal layer and excludes the second metal layer, and extends from the gate line. The input electrode or the output electrode includes a second metal layer and excludes the first metal layer. The input electrode extends from the data line. The pixel electrode is electrically connected to the output electrode of the switching element through a first contact hole, and includes a transparent conductive layer.

Abstract translation: 显示基板包括基底基板，开关元件，栅极线，数据线和像素电极。 栅极线和数据线中的每一个包括第一金属层和直接在第一金属层上的第二金属层。 开关元件在基底基板上，并且包括控制电极和输入电极或输出电极。 控制电极包括第一金属层，并且不包括第二金属层，并且从栅极线延伸。 输入电极或输出电极包括第二金属层，并且不包括第一金属层。 输入电极从数据线延伸。 像素电极通过第一接触孔电连接到开关元件的输出电极，并且包括透明导电层。

公开(公告)号：US20130105826A1

公开(公告)日：2013-05-02

申请号：US13619120

申请日：2012-09-14

Applicant: Jung-Kyu Lee ,  Yoon-Ho Khang ,  Se-Hwan Yu ,  Cheol-Kyu Kim ,  Yong-Su Lee ,  Chong-Sup Chang ,  Sang-Ho Park ,  Su-Hyoung Kang ,  Hyun-Jae Na ,  Young-Ki Shin

Inventor： Jung-Kyu Lee ,  Yoon-Ho Khang ,  Se-Hwan Yu ,  Cheol-Kyu Kim ,  Yong-Su Lee ,  Chong-Sup Chang ,  Sang-Ho Park ,  Su-Hyoung Kang ,  Hyun-Jae Na ,  Young-Ki Shin

IPC: H01L33/08

CPC classification number: H01L27/124 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/1288

Abstract: A display substrate includes a base substrate, a switching element, a gate line, a data line and a pixel electrode. Each of the gate line and the data line includes a first metal layer, and a second metal layer directly on the first metal layer. The switching element is on the base substrate, and includes a control electrode and an input electrode or an output electrode. The control electrode includes the first metal layer and excludes the second metal layer, and extends from the gate line. The input electrode or the output electrode includes a second metal layer and excludes the first metal layer. The input electrode extends from the data line. The pixel electrode is electrically connected to the output electrode of the switching element through a first contact hole, and includes a transparent conductive layer.

Abstract translation: 显示基板包括基底基板，开关元件，栅极线，数据线和像素电极。 栅极线和数据线中的每一个包括第一金属层和直接在第一金属层上的第二金属层。 开关元件在基底基板上，并且包括控制电极和输入电极或输出电极。 控制电极包括第一金属层，并且不包括第二金属层，并且从栅极线延伸。 输入电极或输出电极包括第二金属层，并且不包括第一金属层。 输入电极从数据线延伸。 像素电极通过第一接触孔电连接到开关元件的输出电极，并且包括透明导电层。

公开(公告)号：US08334156B2

公开(公告)日：2012-12-18

申请号：US12648787

申请日：2009-12-29

Applicant: Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

Inventor： Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

IPC: H01L21/205

CPC classification number: H01L29/2003 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02664 ,  H01L33/0075

Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 μm. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.

Abstract translation: 氮化物半导体单晶衬底，其制造方法和使用其的垂直氮化物半导体器件的制造方法。 根据本发明的一个方面，在氮化物半导体单晶衬底中，沿着厚度方向分割上部和下部区域，所述氮化物单晶衬底的厚度至少为100μm。 这里，上部区域的掺杂浓度为下部区域的5倍以上。 优选地，上部区域中的基板的顶表面具有Ga极性。 此外，根据本发明的具体实施例，下部区域有意地未掺杂，并且上部区域是n掺杂的。 优选地，上部区域和下部区域中的每一个具有在厚度方向上基本相同的掺杂浓度。

公开(公告)号：US20090050869A1

公开(公告)日：2009-02-26

申请号：US12073499

申请日：2008-03-06

Applicant: Cheol-kyu Kim ,  Yoon-ho Khang ,  Tae-yon Lee

Inventor： Cheol-kyu Kim ,  Yoon-ho Khang ,  Tae-yon Lee

IPC: H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided is a phase-change random access memory (PRAM). The PRAM includes a bottom electrode, a bottom electrode contact layer, which is formed on one area of the bottom electrode, and an insulating layer, which is formed on a side of the bottom electrode contact layer, a phase-change layer, which is formed on the bottom electrode contact layer and the insulating layer and is formed of a phase-change material having a crystallization temperature between 100° C. and 150° C., and a top electrode, which is formed on the phase-change layer.

Abstract translation: 提供了相变随机存取存储器（PRAM）。 PRAM包括底电极，底电极接触层，其形成在底电极的一个区域上，绝缘层形成在底电极接触层的一侧，相变层 形成在底部电极接触层和绝缘层上，并且由结晶温度在100℃至150℃之间的相变材料和形成在相变层上的顶部电极形成。

公开(公告)号：US20050099853A1

公开(公告)日：2005-05-12

申请号：US10877557

申请日：2004-06-24

Applicant: Cheol-Kyu Kim ,  Ja-Seung Gou

Inventor： Cheol-Kyu Kim ,  Ja-Seung Gou

IPC: G11C7/00 ,  G11C7/20 ,  G11C8/12

CPC classification number: G11C7/20 ,  G11C8/12

Abstract: An apparatus, included in a semiconductor memory device, for generating a bank control signal, includes a logic block for receiving an internal precharge signal and a power-up signal and outputting a first signal; and a latch block for latching an internal active signal and the first signal in order to generate the bank control signal.

Abstract translation: 包括在半导体存储器件中的用于产生存储体控制信号的装置包括：用于接收内部预充电信号和上电信号并输出​​第一信号的逻辑块; 以及用于锁存内部有效信号和第一信号的锁存块，以便产生存储体控制信号。