公开(公告)号：US08614132B2

公开(公告)日：2013-12-24

申请号：US13240025

申请日：2011-09-22

Applicant: Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

Inventor： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC: H01L21/336

CPC classification number: H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US08580641B2

公开(公告)日：2013-11-12

申请号：US13191297

申请日：2011-07-26

Applicant: Wei-Yuan Lu ,  Kuan-Chung Chen ,  Chun-Fai Cheng

Inventor： Wei-Yuan Lu ,  Kuan-Chung Chen ,  Chun-Fai Cheng

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/70 ,  H01L21/8234

CPC classification number: H01L27/11 ,  H01L21/28176 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7827

Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.

公开(公告)号：US08535998B2

公开(公告)日：2013-09-17

申请号：US12720075

申请日：2010-03-09

Applicant: Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

Inventor： Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC: H01L21/338

CPC classification number: H01L29/7833 ,  H01L21/76834 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7836

Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.

Abstract translation: 本公开公开了一种用于制造栅极结构的示例性方法，其包括在衬底上沉积和图案化虚拟氧化物层和伪栅极电极层; 围绕所述虚拟氧化物层和所述伪栅极电极层，具有牺牲层; 用含氮介电层围绕牺牲层; 用层间介质层包围含氮介电层; 去除所述伪栅电极层; 去除虚拟氧化物层; 去除所述牺牲层以在所述含氮介电层中形成开口; 并沉积栅极电介质; 并沉积栅电极。

公开(公告)号：US08482079B2

公开(公告)日：2013-07-09

申请号：US13161031

申请日：2011-06-15

Applicant: Chun-Fai Cheng ,  Li-Ping Huang ,  Ka-Hing Fung

Inventor： Chun-Fai Cheng ,  Li-Ping Huang ,  Ka-Hing Fung

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66666 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed device comprises a gate structure over a substrate and defining a channel region in the substrate, an epitaxial feature with a first dopant in the substrate, and an epitaxial source/drain feature with a second dopant in the substrate. The epitaxial source/drain feature is farther from the channel region than the epitaxial feature is. The second dopant has an electrical carrier type opposite to the first dopant.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的器件包括在衬底上的栅极结构并且限定衬底中的沟道区，在衬底中具有第一掺杂剂的外延特征以及在衬底中具有第二掺杂剂的外延源极/漏极特征。 外延源极/漏极特征比沟道区域远离外延特征。 第二掺杂剂具有与第一掺杂剂相反的电载体。

公开(公告)号：US20120091540A1

公开(公告)日：2012-04-19

申请号：US12984703

申请日：2011-01-05

Applicant: Chun-Fai CHENG ,  Ka-Hing FUNG ,  Li-Ping HUANG ,  Wei-Yuan LU

Inventor： Chun-Fai CHENG ,  Ka-Hing FUNG ,  Li-Ping HUANG ,  Wei-Yuan LU

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636

Abstract: In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity

Abstract translation: 在p型场效应晶体管中，在衬底的顶表面上形成一对衬垫。 通道凹腔包括在一对间隔件之间的衬底顶表面中的凹陷。 栅极叠层在通道凹槽中具有底部，并且在沟槽凹槽内延伸出顶部。 源极/漏极（S / D）凹腔具有底表面和位于衬底顶表面下方的侧壁。 S / D凹陷腔具有在栅极叠层下方延伸的部分。 应变材料填充S / D凹槽

公开(公告)号：US09847225B2

公开(公告)日：2017-12-19

申请号：US13296908

申请日：2011-11-15

Applicant: Chun-Fai Cheng ,  An-Shen Chang ,  Hui-Min Lin ,  Tsz-Mei Kwok ,  Hsien-Ching Lo

Inventor： Chun-Fai Cheng ,  An-Shen Chang ,  Hui-Min Lin ,  Tsz-Mei Kwok ,  Hsien-Ching Lo

IPC: H01L29/772 ,  H01L21/336 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02639 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.

公开(公告)号：US08928094B2

公开(公告)日：2015-01-06

申请号：US12875834

申请日：2010-09-03

Applicant: Chun-Fai Cheng ,  Ka-Hing Fung ,  Shyh-Wei Wang ,  Chin-Te Su

Inventor： Chun-Fai Cheng ,  Ka-Hing Fung ,  Shyh-Wei Wang ,  Chin-Te Su

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7848

Abstract: The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.

Abstract translation: 本公开提供半导体器件及其制造方法，其中半导体器件具有应变的不对称源极和漏极区域。 制造半导体器件的方法包括提供衬底并在衬底上形成多晶硅叠层。 掺杂剂以垂直于衬底的约10°至约25°的注入角度注入衬底中。 邻近衬底上的多晶硅叠层形成间隔物。 源极区和漏极区被蚀刻在衬底中。 应变源极层和应变漏极层分别沉积在衬底中的蚀刻源极和漏极区域中，使得源极区域和漏极区域相对于多晶硅栅极叠层是不对称的。 多晶硅堆叠从衬底去除，并且使用去除多晶硅叠层的最后工艺形成高k金属栅极。

公开(公告)号：US08709897B2

公开(公告)日：2014-04-29

申请号：US12956090

申请日：2010-11-30

Applicant: Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

Inventor： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/165 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.

Abstract translation: 用于形成高性能应变源极 - 漏极结构的方法包括在衬底上形成栅极结构并且形成靠近栅极结构的凹穴注入区域。 隔板与门结构相邻形成。 干蚀刻形成具有第一轮廓的凹部; 湿蚀刻将凹槽放大到第二轮廓; 并且热蚀刻将凹槽放大到第三轮廓。 然后在具有第三轮廓的凹槽中形成源极 - 漏极结构。

公开(公告)号：US08558289B2

公开(公告)日：2013-10-15

申请号：US12795088

申请日：2010-06-07

Applicant: Chun-Fai Cheng ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Fung Ka Hing

Inventor： Chun-Fai Cheng ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Fung Ka Hing

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate.

Abstract translation: 晶体管包括设置在衬底上的栅电极。 至少一个复合应变结构邻近栅电极下方的沟道设置。 所述至少一个复合应变结构包括所述基底内的第一应变区。 第二应变区设置在第一应变区上。 第二应变区域的至少一部分设置在衬底内。

公开(公告)号：US20120319203A1

公开(公告)日：2012-12-20

申请号：US13161031

申请日：2011-06-15

Applicant: Chun-Fai CHENG ,  Li-Ping HUANG ,  Ka-Hing FUNG

Inventor： Chun-Fai CHENG ,  Li-Ping HUANG ,  Ka-Hing FUNG

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66666 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed device comprises a gate structure over a substrate and defining a channel region in the substrate, an epitaxial feature with a first dopant in the substrate, and an epitaxial source/drain feature with a second dopant in the substrate. The epitaxial source/drain feature is farther from the channel region than the epitaxial feature is. The second dopant has an electrical carrier type opposite to the first dopant.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的器件包括在衬底上的栅极结构并且限定衬底中的沟道区，在衬底中具有第一掺杂剂的外延特征以及在衬底中具有第二掺杂剂的外延源极/漏极特征。 外延源极/漏极特征比沟道区域远离外延特征。 第二掺杂剂具有与第一掺杂剂相反的电载体。