公开(公告)号：US20120314391A1

公开(公告)日：2012-12-13

申请号：US13183452

申请日：2011-07-15

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

IPC: H05K7/12 ,  H05K7/00

CPC classification number: H05K1/0231 ,  H05K1/0222 ,  H05K2201/09618

Abstract: A circuit board includes a base board defining a number of via holes, a power supply connection unit, a load connection unit, and at least one capacitor connection unit(s). Each of the at least one capacitor connection unit(s) includes two capacitor connectors, and one of the two capacitor connectors is positioned nearer to the power supply connection unit and farther away from the load connection unit than the other. The via holes are divided into at least one group(s) corresponding to each of the capacitor connection unit(s), and all of the via holes in each of the group(s) are equidistantly positioned along a semicircle arc surrounding the capacitor connector of the capacitor connection unit corresponding to the group that is positioned nearer to the power supply connection unit.

Abstract translation: 电路板包括限定多个通孔的基板，电源连接单元，负载连接单元和至少一个电容器连接单元。 所述至少一个电容器连接单元中的每一个包括两个电容器连接器，并且所述两个电容器连接器中的一个位于更靠近所述电源连接单元的位置，并且远离所述负载连接单元。 通孔被分成与电容器连接单元中的每一个相对应的至少一个组，并且每个组中的所有通路孔沿着围绕电容器连接器的半圆弧等距定位 的电容器连接单元对应于位于更靠近电源连接单元的组的电容器连接单元。

公开(公告)号：US20120278784A1

公开(公告)日：2012-11-01

申请号：US13315291

申请日：2011-12-09

Applicant: DAN-CHEN WU ,  SHOU-KUO HSU ,  CHENG-HSIEN LEE ,  CHUN-JEN CHEN

Inventor： DAN-CHEN WU ,  SHOU-KUO HSU ,  CHENG-HSIEN LEE ,  CHUN-JEN CHEN

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a power line is selected from a layout diagram of the PCB. The method searches for one or more signal lines which are overlapping with the selected power line from the layout diagram of the PCB. The method further locates attribute data of the searched signal lines and the selected power line in the layout diagram of the PCB, and displays the attribute data of the searched signal lines and the selected power line on a display device of the electronic device.

Abstract translation: 在使用电子设备检查印刷电路板（PCB）的布局的方法中，从PCB的布局图中选择电力线。 该方法从PCB的布局图搜索与所选择的电力线重叠的一条或多条信号线。 该方法进一步在PCB的布局图中定位搜索到的信号线和所选电力线的属性数据，并将所搜索的信号线和所选电力线的属性数据显示在电子设备的显示装置上。

公开(公告)号：US20120217628A1

公开(公告)日：2012-08-30

申请号：US13034263

申请日：2011-02-24

Applicant: You-Hua CHOU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Perre KAO

Inventor： You-Hua CHOU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Perre KAO

IPC: H01L23/52 ,  H01L21/44

CPC classification number: H01L23/473 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/48 ,  H01L23/488 ,  H01L24/11 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/11849 ,  H01L2224/16145 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

Abstract: The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps.

Abstract translation: 用于形成连接到本文所述的冷却装置（或散热器）的金属凸块的机构使得具有装置的基板能够更有效地散发产生的热量。 此外，金属凸块允许定制凹凸设计以满足不同芯片的需要。 此外，半导体芯片和冷却装置之间的金属凸块的使用能够通过在凸块之间传递冷却流体而进行先进的冷却。

公开(公告)号：US08239815B2

公开(公告)日：2012-08-07

申请号：US12701677

申请日：2010-02-08

Applicant: Hsien-Chuan Liang ,  Shen-Chun Li ,  Chun-Jen Chen ,  Shou-Kuo Hsu ,  Duen-Yi Ho ,  Yung-Chieh Chen

Inventor： Hsien-Chuan Liang ,  Shen-Chun Li ,  Chun-Jen Chen ,  Shou-Kuo Hsu ,  Duen-Yi Ho ,  Yung-Chieh Chen

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A system and method for inspecting layout of a printed circuit board (PCB) provides a graphical user interface (GUI). The GUI displays a layout of the PCB. High side pins of a pulse width modulation (PWM) controller and a component connected to a high side pin are found. If the component is a metallic oxide semiconductor field effect transistor (MOSFET), the system calculate absolute a linear distance and a trace distance between a source pin of the MOSFET and a capacitor pin of a coupling capacitor connected to the source pin. If the linear distance, the trace distance and a capacitance of the coupling capacitor accord with a layout standard, the layout of the PCB is determined to be up to standard.

Abstract translation: 用于检查印刷电路板（PCB）的布局的系统和方法提供图形用户界面（GUI）。 GUI显示PCB的布局。 发现脉冲宽度调制（PWM）控制器的高端引脚和连接到高端引脚的元件。 如果组件是金属氧化物半导体场效应晶体管（MOSFET），则系统计算绝缘线性距离和MOSFET的源极引脚与连接到源极引脚的耦合电容的电容引脚之间的走线距离。 如果线性距离，迹线距离和耦合电容的电容符合布局标准，则PCB的布局被确定为达到标准。

公开(公告)号：US20120176110A1

公开(公告)日：2012-07-12

申请号：US13008037

申请日：2011-01-18

Applicant: DUEN-YI HO ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU ,  TSUNG-SHENG HUANG

Inventor： DUEN-YI HO ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU ,  TSUNG-SHENG HUANG

IPC: G05F1/00

CPC classification number: H02M3/156 ,  H02M2001/0009

Abstract: A voltage regulating circuit includes a pulse width modulation controller, a current sense circuit, a voltage feedback circuit, and a gain-and-bias circuit. The current sense circuit includes an inductor and a capacitor. The voltage feedback circuit includes first and second resistors. The gain-and-bias circuit includes an operational amplifier. A first terminal of the capacitor is connected to an inverting input terminal of the operational amplifier through a third resistor. A second terminal of the capacitor is connected to a non-inverting input terminal of the operational amplifier through a fourth resistor. The inverting input terminal of the amplifier is connected to an output terminal of the operational amplifier through a fifth resistor. The non-inverting input terminal of the operational amplifier is grounded through a sixth resistor. The output terminal of the operational amplifier is connected to the node between the first and second resistors through a seventh resistor.

Abstract translation: 电压调节电路包括脉宽调制控制器，电流检测电路，电压反馈电路和增益与偏置电路。 电流检测电路包括电感器和电容器。 电压反馈电路包括第一和第二电阻器。 增益和偏置电路包括运算放大器。 电容器的第一端子通过第三电阻器连接到运算放大器的反相输入端子。 电容器的第二端子通过第四电阻器连接到运算放大器的非反相输入端子。 放大器的反相输入端通过第五个电阻连接到运算放大器的输出端。 运算放大器的非反相输入端通过第六个电阻接地。 运算放大器的输出端通过第七电阻连接到第一和第二电阻之间的节点。

公开(公告)号：US08199522B2

公开(公告)日：2012-06-12

申请号：US12497709

申请日：2009-07-06

Applicant: Shou-Kuo Hsu ,  Chun-Jen Chen

Inventor： Shou-Kuo Hsu ,  Chun-Jen Chen

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0231 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/0969 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A printed circuit board includes a first signal layer, a first reference layer, a second reference layer, and a second signal layer. An integrated circuit mounted on the first signal layer includes a power supply terminal connected to a first power supply via. The second signal layer includes a filter and a power supply wire. The filter includes a power terminal connected to the first power supply via, and a ground terminal connected to the second reference layer. The first power supply via is connected to the first reference layer through the power supply wire and a second power supply via. A void defined in the second reference layer is at least partially vertically overlapping with the power supply wire, and enables the first reference layer to function as a reference plane for the power supply wire, to increase impedance of the power supply wire.

Abstract translation: 印刷电路板包括第一信号层，第一参考层，第二参考层和第二信号层。 安装在第一信号层上的集成电路包括连接到第一电源通路的电源端子。 第二信号层包括滤波器和电源线。 滤波器包括连接到第一电源通孔的电源端子和连接到第二参考层的接地端子。 第一电源通孔通过电源线和第二电源通孔连接到第一参考层。 限定在第二参考层中的空隙至少部分地与电源线垂直重叠，并且使得第一参考层能够用作电源线的参考平面，以增加电源线的阻抗。

公开(公告)号：US08068553B2

公开(公告)日：2011-11-29

申请号：US12633895

申请日：2009-12-09

Applicant: Po-Chuan Hsieh ,  Chun-Jen Chen ,  Chien-Hung Liu ,  Yu-Chang Pai ,  Shou-Kuo Hsu

Inventor： Po-Chuan Hsieh ,  Chun-Jen Chen ,  Chien-Hung Liu ,  Yu-Chang Pai ,  Shou-Kuo Hsu

IPC: H04L7/02 ,  H04B7/02

CPC classification number: H04B17/0085 ,  H04B17/21 ,  H04B17/23 ,  H04B17/327 ,  H04L1/0668

Abstract: A performance evaluation system for a multiple-input multiple-output (MIMO) antenna system receives simulation parameters from an input device, and simulates a MIMO antenna system accordingly. A method, also provided, further evaluates performance of the simulated MIMO antenna system when a series of radio frequency (RF) signals are transmitted through the MIMO antenna system, and displays a performance analysis result of the MIMO antenna system on a display device for evaluation of the performance of the simulated MIMO antenna system.

Abstract translation: 用于多输入多输出（MIMO）天线系统的性能评估系统从输入设备接收模拟参数，并相应地模拟MIMO天线系统。 还提供了一种方法，当通过MIMO天线系统传输一系列射频（RF）信号时，进一步评估模拟MIMO天线系统的性能，并且在用于评估的显示装置上显示MIMO天线系统的性能分析结果 的模拟MIMO天线系统的性能。

公开(公告)号：US20110094787A1

公开(公告)日：2011-04-28

申请号：US12647431

申请日：2009-12-25

Applicant: YING-TSO LAI ,  CHUN-JEN CHEN ,  YU-CHANG PAI ,  PEI-CHUN LIN ,  CHIN-HUI CHEN ,  HSIAO-PING HUANG

Inventor： YING-TSO LAI ,  CHUN-JEN CHEN ,  YU-CHANG PAI ,  PEI-CHUN LIN ,  CHIN-HUI CHEN ,  HSIAO-PING HUANG

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K3/3447 ,  H05K2201/062 ,  H05K2201/09036 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2203/0242 ,  Y10T29/49155

Abstract: A printed circuit board includes a layer. A layer of copper is covered on a surface of the layer. A through hole passes through the printed circuit board. A number of thermal engravings are defined in the layer around the through hole. Each thermal engraving is a groove defined in the surface of the layer, without covered with the layer of copper. The number of thermal engravings are not in contact with each other.

Abstract translation: 印刷电路板包括一层。 铜层被覆盖在该层的表面上。 通孔穿过印刷电路板。 在通孔周围的层中限定了许多热雕刻。 每个热雕刻是在层的表面中限定的凹槽，而不被铜层覆盖。 热雕刻的数量彼此不接触。

公开(公告)号：US20110047524A1

公开(公告)日：2011-02-24

申请号：US12701677

申请日：2010-02-08

Applicant: HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  CHUN-JEN CHEN ,  SHOU-KUO HSU ,  DUEN-YI HO ,  YUNG-CHIEH CHEN

Inventor： HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  CHUN-JEN CHEN ,  SHOU-KUO HSU ,  DUEN-YI HO ,  YUNG-CHIEH CHEN

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A system and method for inspecting layout of a printed circuit board (PCB) provides a graphical user interface (GUI). The GUI displays a layout of the PCB. High side pins of a pulse width modulation (PWM) controller and a component connected to a high side pin are found. If the component is a metallic oxide semiconductor field effect transistor (MOSFET), the system calculate absolute a linear distance and a trace distance between a source pin of the MOSFET and a capacitor pin of a coupling capacitor connected to the source pin. If the linear distance, the trace distance and a capacitance of the coupling capacitor accord with a layout standard, the layout of the PCB is determined to be up to standard.

Abstract translation: 用于检查印刷电路板（PCB）的布局的系统和方法提供图形用户界面（GUI）。 GUI显示PCB的布局。 发现脉冲宽度调制（PWM）控制器的高端引脚和连接到高端引脚的元件。 如果组件是金属氧化物半导体场效应晶体管（MOSFET），则该系统计算绝缘线性距离和MOSFET的源极引脚与连接到源极引脚的耦合电容的电容引脚之间的走线距离。 如果线性距离，迹线距离和耦合电容的电容符合布局标准，则PCB的布局被确定为达到标准。

公开(公告)号：US20110012426A1

公开(公告)日：2011-01-20

申请号：US12551463

申请日：2009-08-31

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO

IPC: H02J1/00 ,  G06F17/50

CPC classification number: G06F1/26 ,  G06F17/50 ,  H02J1/00 ,  Y10T307/25 ,  Y10T307/555

Abstract: A power supply system includes a power supply, a daughterboard, and a motherboard. Output currents of power connectors of the motherboard and impedances of copper foils between every two adjacent power connectors of the motherboard are obtained via simulation. A voltage of one power connector of the motherboard is predetermined. Therefore, desired impedances of copper foils between VRM connectors and corresponding power connectors on the daughter board are determined via calculations, to make currents passing through the power connectors of the motherboard equal to each other.

Abstract translation: 电源系统包括电源，子板和主板。 母板电源连接器的输出电流和母板每两个相邻电源连接器之间铜箔的阻抗通过仿真获得。 母板的一个电源连接器的电压是预先确定的。 因此，通过计算确定VRM连接器与子板上相应的电源连接器之间的铜箔的期望阻抗，以使通过主板的电源连接器的电流彼此相等。