公开(公告)号：US20060043987A1

公开(公告)日：2006-03-02

申请号：US11269047

申请日：2005-11-07

Applicant: Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

Inventor： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

IPC: G01R31/02

CPC classification number: G01R31/04 ,  G01R1/0408 ,  G01R1/06772 ,  G01R27/2617 ,  G01R31/2896 ,  H01L24/73 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

Abstract translation: 提供了用于使用网络分析仪与同轴测试探针一起测量任何类型或配置的集成电路封装中的互耦合的可能性的方法。 简单，低成本的测试夹具和测试方法可用于测量集成电路封装的一个或多个I / O引线的寄生电容和电感，所测量的寄生电容和电感提供了集成电路的易感性指示 电路封装以在封装的电引线之间或电引线和集成电路封装的其它部件之间相互耦合。

公开(公告)号：US20050024039A1

公开(公告)日：2005-02-03

申请号：US10927578

申请日：2004-08-25

Applicant: William Casey ,  David Cuthbert ,  Olivia McGrew

Inventor： William Casey ,  David Cuthbert ,  Olivia McGrew

IPC: G01R31/28 ,  H05K1/02 ,  H05K1/11 ,  G01R1/00

CPC classification number: H05K1/0268 ,  G01R31/2889 ,  H05K1/112 ,  H05K2201/09781

Abstract: An integrated circuit characterization printed circuit board and method are provided for improving the uniformity of impedance introduced by a test fixture across all of the pins of an integrated circuit device. The printed circuit board includes an array of substantially similar test contacts numbering greater than the pins of the integrated circuit device. The array of test contacts includes an active portion configured for electrically coupling with the corresponding pins on the integrated circuit device and an inactive portion adjacent to the active portion and electrically coupled to a reference signal on the printed circuit board.

Abstract translation: 提供了一种集成电路表征印刷电路板和方法，用于改善由集成电路器件的所有引脚上的测试夹具引入的阻抗的均匀性。 印刷电路板包括大致类似的测试触头的阵列，编号大于集成电路器件的引脚。 测试触点阵列包括被配置用于与集成电路器件上的相应引脚电耦合的有源部分和与有源部分相邻的非活动部分，并电耦合到印刷电路板上的参考信号。

公开(公告)号：US06675313B2

公开(公告)日：2004-01-06

申请号：US10329494

申请日：2002-12-27

Applicant: David Cuthbert

Inventor： David Cuthbert

IPC: G06F104

CPC classification number: H05K1/0248 ,  G06F1/10 ,  H05K1/0293 ,  H05K3/027 ,  H05K2201/09263 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/0979 ,  H05K2203/095 ,  H05K2203/107 ,  H05K2203/1115 ,  H05K2203/1338 ,  H05K2203/171 ,  H05K2203/175

Abstract: An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.

Abstract translation: 描述了一种用于减少包括互连第一节点和第二节点的多个导电迹线的印刷电路板上的定时偏移的装置和方法。 至少一个部分从至少一个印刷电路板迹线移除，从而切断迹线并防止从第一节点传递到第二节点的信号不跟随切断的迹线。 以这种方式，可以调整信号路径长度以减少电路中的定时偏差。 通过使用激光，CVD，路由器，等离子体或者通过使足够的电流通过弱化区域从迹线中去除部分。

公开(公告)号：US20070054550A1

公开(公告)日：2007-03-08

申请号：US11278541

申请日：2006-04-03

Applicant: David Cuthbert ,  Larry Rogel ,  Matthew Page ,  James Page

Inventor： David Cuthbert ,  Larry Rogel ,  Matthew Page ,  James Page

IPC: H01R13/648

CPC classification number: H01R29/00 ,  H01R27/02 ,  H01R2201/04 ,  H01R2201/06

Abstract: An apparatus which provides the ability to charge or power multiple devices from multiple different power sources, and to communicate electronic data to and from one of the devices. The apparatus utilizes simple construction, requiring no active electronics, thereby reducing the cost of production and the reliability of the device. The apparatus employs a single USB connection cable with connectors on both ends and a second power-only cable and connector which is connected to the power wires of the USB cable and thereby is able to power a second portable device from a single USB port. USB master provide sufficient power for two average portable devices without additional circuitry. Moreover, restricting the data path to only one device also eliminates the need for USB hub circuitry. Finally, greater end user flexibility is provided by using a USB male connector as the source of the data and power connection, a USB female connector for the output of the data and power connection, and a standard barrel-type power connector for the power-only output connection. Having two different output connectors ensures that the user will not confuse the two connectors.

Abstract translation: 一种提供从多个不同电源对多个设备进行充电或供电的能力以及将电子数据传送到设备之一或从设备之一传送电子数据的设备。 该设备采用简单的结构，不需要有源电子元件，从而降低了生产成本和设备的可靠性。 该装置采用单个USB连接电缆，其两端具有连接器，以及第二电源电缆和连接器，其连接到USB电缆的电源线，从而能够从单个USB端口为第二便携式设备供电。 USB主机为两个平均的便携式设备提供足够的电力，无需额外的电路。 而且，将数据路径限制在一个设备上也不需要USB集线器电路。 最后，通过使用USB公连接器作为数据和电源连接的来源，提供用于输出数据和电源连接的USB母连接器以及用于电源连接的标准机筒式电源连接器来提供更大的终端用户灵活性， 只输出连接。 具有两个不同的输出连接器可确保用户不会混淆两个连接器。

公开(公告)号：US20050206400A1

公开(公告)日：2005-09-22

申请号：US11142226

申请日：2005-06-01

Applicant: William Casey ,  David Cuthbert ,  Olivia McGrew

Inventor： William Casey ,  David Cuthbert ,  Olivia McGrew

IPC: G01R31/28 ,  H05K1/02 ,  H05K1/11 ,  G01R31/02

CPC classification number: H05K1/0268 ,  G01R31/2889 ,  H05K1/112 ,  H05K2201/09781

Abstract: An integrated circuit characterization printed circuit board and method are provided for improving the uniformity of impedance introduced by a test fixture across all of the pins of an integrated circuit device. The printed circuit board includes an array of substantially similar test contacts numbering greater than the pins of the integrated circuit device. The array of test contacts includes an active portion configured for electrically coupling with the corresponding pins on the integrated circuit device and an inactive portion adjacent to the active portion and electrically coupled to a reference signal on the printed circuit board.

Abstract translation: 提供了一种集成电路表征印刷电路板和方法，用于改善由集成电路器件的所有引脚上的测试夹具引入的阻抗的均匀性。 印刷电路板包括大致类似的测试触头的阵列，编号大于集成电路器件的引脚。 测试触点阵列包括被配置用于与集成电路器件上的相应引脚电耦合的有源部分和与有源部分相邻的非活动部分，并电耦合到印刷电路板上的参考信号。

公开(公告)号：US06322934B1

公开(公告)日：2001-11-27

申请号：US09409115

申请日：1999-09-30

Applicant: John David Cuthbert ,  Feng Jin

Inventor： John David Cuthbert ,  Feng Jin

IPC: G03F900

CPC classification number: G03F7/70466 ,  G03F7/2022

Abstract: A method is for making an integrated circuit on a semiconductor wafer, where the integrated circuit includes circuit features having a desired, relatively small, critical dimension. The method preferably comprises the steps of: designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension. The designing step preferably includes determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift. The method preferably includes steps of fabricating the reticle and using the reticle to make the integrated circuit on the semiconductor wafer based on the plurality of exposure steps. The present invention recognizes that the scaling factor is not a single number, but instead is a non-linear function which is also based upon the shift between exposure steps.

Abstract translation: 一种用于在半导体晶片上制造集成电路的方法，其中集成电路包括具有期望的，相对小的临界尺寸的电路特征。 该方法优选地包括以下步骤：设计包括具有临界尺寸的图案特征的掩模版，以形成相应的电路特征，基于由多个曝光步骤之间移动而定义的重叠区域，使得电路特征具有期望的，相对较小的， 关键维度。 设计步骤优选地包括确定缩放因子函数，用于将图案特征的临界尺度和向电路特征的期望临界尺度的偏移相关联，同时考虑到比例因子函数也是该偏移的函数。 该方法优选包括以下步骤：基于多个曝光步骤，制造掩模版并使用掩模版将集成电路制成在半导体晶片上。 本发明认识到缩放因子不是单个数字，而是基于曝光步骤之间的偏移的非线性函数。

公开(公告)号：US20070290741A1

公开(公告)日：2007-12-20

申请号：US11849043

申请日：2007-08-31

Applicant: Leonard Forbes ,  David Cuthbert

Inventor： Leonard Forbes ,  David Cuthbert

IPC: H03F1/48

CPC classification number: H03F3/005 ,  H03F1/26 ,  H03F1/38 ,  H03F3/45183 ,  H03F2203/45166 ,  H03F2203/45224 ,  H03F2203/45514 ,  H03F2203/45551 ,  H03F2203/45674 ,  H03F2203/45722

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a CMOS amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion. This feedback proportion may be configured to maintain a stable gain of the switched capacitor amplifier and increase a signal-to-noise ratio of the switched capacitor amplifier, even with the switched capacitor amplifier in a positive feedback arrangement

Abstract translation: 本发明包括开关电容放大器，其包括对半导体器件的正反馈，晶圆及其结合的系统以及使用正反馈放大信号的方法，同时保持稳定的增益并产生改善的信噪比。 一个实施例包括具有CMOS放大器，馈入开关电容器和反馈开关电容器的开关电容放大器。 馈入开关电容将输入信号耦合到CMOS放大器的非反相输入。 类似地，反馈开关电容器将放大器输出耦合到非反相输入端以产生正反馈回路。 反馈开关电容器相对于馈入开关电容器的电容的电容包括反馈比例。 该反馈比例可以被配置为保持开关电容放大器的稳定增益并且增加开关电容放大器的信噪比，即使开关电容放大器处于正反馈布置

公开(公告)号：US20070030059A1

公开(公告)日：2007-02-08

申请号：US11196117

申请日：2005-08-03

Applicant: Leonard Forbes ,  David Cuthbert

Inventor： Leonard Forbes ,  David Cuthbert

IPC: H03F1/02

CPC classification number: H03F3/005 ,  H03F1/26 ,  H03F1/38 ,  H03F3/45183 ,  H03F2203/45166 ,  H03F2203/45224 ,  H03F2203/45514 ,  H03F2203/45551 ,  H03F2203/45674 ,  H03F2203/45722

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback, semiconductor devices, wafers and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a Complementary Metal Oxide Semiconductor (CMOS) amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor operably couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor operably couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion. This feedback proportion may be configured to maintain a stable gain of the switched capacitor amplifier and increase a signal-to-noise ratio of the switched capacitor amplifier, even with the switched capacitor amplifier configured in a positive feedback arrangement.

Abstract translation: 本发明包括开关电容放大器，其包括正反馈，半导体器件，晶圆及其结合的系统，以及使用正反馈放大信号的方法，同时保持稳定的增益并产生改善的信噪比。 一个实施例包括开关电容放大器，其包括互补金属氧化物半导体（CMOS）放大器，馈入开关电容器和反馈开关电容器。 馈入开关电容器将输入信号可操作地耦合到CMOS放大器的非反相输入端。 类似地，反馈开关电容器可操作地将放大器输出耦合到非反相输入端以产生正反馈回路。 反馈开关电容器相对于馈入开关电容器的电容的电容包括反馈比例。 该反馈比例可以被配置为保持开关电容放大器的稳定增益，并增加开关电容放大器的信噪比，即使开关电容放大器以正反馈布置配置。

公开(公告)号：US20060250871A1

公开(公告)日：2006-11-09

申请号：US11485218

申请日：2006-07-12

Applicant: Leonard Forbes ,  David Cuthbert

Inventor： Leonard Forbes ,  David Cuthbert

IPC: G11C7/00

CPC classification number: G11C27/026 ,  G11C7/062 ,  G11C11/4091

Abstract: A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line when a signal representing a data bit is present in the bit line. The differential amplifier amplifies the difference between the signal voltage and the reference voltage.

公开(公告)号：US20060044907A1

公开(公告)日：2006-03-02

申请号：US10931786

申请日：2004-09-01

Applicant: Leonard Forbes ,  David Cuthbert

Inventor： Leonard Forbes ,  David Cuthbert

IPC: G11C7/02

CPC classification number: G11C27/026 ,  G11C7/062 ,  G11C11/4091

Abstract: A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line when a signal representing a data bit is present in the bit line. The differential amplifier amplifies the difference between the signal voltage and the reference voltage.

Abstract translation: 存储读出放大器包括一个采样和保持电路，后跟一个差分放大器。 当在位线中存在表示数据位的信号时，采样和保持电路在存储器电路的位线上对基准电压进行采样，当读出放大器被复位时，信号电压位于同一位线上。 差分放大器放大信号电压和参考电压之间的差值。