公开(公告)号：US06639266B1

公开(公告)日：2003-10-28

申请号：US09651470

申请日：2000-08-30

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L27108

CPC classification number: H01L28/91 ,  H01L21/31056 ,  H01L27/10855 ,  H01L28/84

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The methods further include modifying the removal selectivity of the surface material relative to material protected by the localized masking. Modification of the removal selectivity eases or quickens removal of the surface material. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 所述方法还包括改变表面材料相对于通过局部掩蔽保护的材料的去除选择性。 去除选择性的改性缓和或加快了表面材料的去除。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US06573554B2

公开(公告)日：2003-06-03

申请号：US09912151

申请日：2001-07-24

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L2978

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

公开(公告)号：US06316370B1

公开(公告)日：2001-11-13

申请号：US09644699

申请日：2000-08-24

Applicant: Garry A. Mercaldi ,  Donald L. Yates

Inventor： Garry A. Mercaldi ,  Donald L. Yates

IPC: H01L21461

CPC classification number: H01L21/32134

Abstract: The present invention provides an etching composition which includes a polyhydric alcohol in combination with two inorganic acids. Preferably the etching composition of the present invention is a mixture of a glycol, nitric acid and hydrofluoric acid, with propylene glycol being preferred. The etching composition of the present invention achieves a selectivity of greater than 70:1, doped material to undoped material. The present invention provides an etching formulation which has increased selectivity of doped polysilicon to undoped polysilicon and provides an efficient integrated circuit fabrication process without requiring time consuming and costly processing modifications to the etching apparatus or production apparatus.

Abstract translation: 本发明提供一种蚀刻组合物，其包含与两种无机酸组合的多元醇。 优选地，本发明的蚀刻组合物是二醇，硝酸和氢氟酸的混合物，优选丙二醇。 本发明的蚀刻组合物实现大于70:1的掺杂材料对未掺杂材料的选择性。 本发明提供了一种蚀刻配方，其具有增加掺杂多晶硅对未掺杂多晶硅的选择性，并且提供了有效的集成电路制造工艺，而不需要对蚀刻设备或生产设备进行耗时且昂贵的处理修改。

公开(公告)号：US08492288B2

公开(公告)日：2013-07-23

申请号：US12136661

申请日：2008-06-10

Applicant: Janos Fucsko ,  Niraj B. Rana ,  Sandra Tagg ,  Robert J. Hanson ,  Gundu M. Sabde ,  Donald L. Yates ,  Patrick M. Flynn ,  Prashant Raghu ,  Kyle Grant

Inventor： Janos Fucsko ,  Niraj B. Rana ,  Sandra Tagg ,  Robert J. Hanson ,  Gundu M. Sabde ,  Donald L. Yates ,  Patrick M. Flynn ,  Prashant Raghu ,  Kyle Grant

IPC: H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  B08B3/00

CPC classification number: H01L21/30604 ,  H01L21/02052 ,  H01L21/31111

Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.

公开(公告)号：US07642157B2

公开(公告)日：2010-01-05

申请号：US11510949

申请日：2006-08-28

Applicant: Donald L Yates ,  Garry A Mercaldi

Inventor： Donald L Yates ,  Garry A Mercaldi

IPC: H01L21/8242

CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

Abstract translation: 提供了形成半导体电路中的电容器的下电极的方法以及通过这些方法形成的电容器。 下电极通过形成纹理化的底层然后在其上沉积导电材料来制造。 在形成下电极的方法的一个实施方案中，通过在容器的绝缘层上沉积包含烃嵌段和含硅嵌段的聚合材料，然后随后将聚合物膜转化为浮雕而形成该组织化层 或通过暴露于UV辐射和臭氧的多孔纳米结构，导致织构化的多孔或缓蚀硅碳化硅膜。 然后将导电材料沉积在纹理化层上，导致下部电极具有上部粗糙表面。 在形成下电极的方法的另一实施例中，通过沉积覆盖的第一和第二导电金属层并退火金属层形成优选构造为周期性网络的表面位错来形成纹理化下层。 然后将导电金属沉积在气相中，并且聚集到构造层的表面位错上，形成岛簇形式的纳米结构。 电容器通过在形成的下电极上沉积介电层并在电介质层上形成上电容器电极来完成。 电容器在制造DRAM单元时特别有用。

公开(公告)号：US07482176B2

公开(公告)日：2009-01-27

申请号：US11705211

申请日：2007-02-12

Applicant: Donald L. Yates ,  Karen T Signorini

Inventor： Donald L. Yates ,  Karen T Signorini

IPC: H01L21/00

CPC classification number: H01L27/222 ,  H01L21/32139 ,  H01L43/12

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract translation: 描述了一种用于形成MRAM位的方法，其包括在集成电路结构上提供覆盖层。 在一个实施例中，覆盖层包括钽。 第一掩模层形成在覆盖层之后，随后是第二掩模层。 第一掩模层和第二掩模层可以通过相同的蚀刻工艺进行蚀刻。 蚀刻第一和第二掩模层。 蚀刻残渣从第一和第二掩模层去除。 然后选择性地去除第一掩模层，并且残留第二掩模层。

公开(公告)号：US07422639B2

公开(公告)日：2008-09-09

申请号：US11188048

申请日：2005-07-22

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B3/04

CPC classification number: H01L21/67034 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67028 ,  H01L21/67057 ,  Y10S134/902

Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.

Abstract translation: 本发明涉及一种在改进的常规气体蚀刻/漂洗或干燥容器中清洗和干燥半导体结构的方法。

公开(公告)号：US07067466B2

公开(公告)日：2006-06-27

申请号：US10187139

申请日：2002-07-01

Applicant: Donald L. Yates ,  Max F. Hineman

Inventor： Donald L. Yates ,  Max F. Hineman

IPC: C09K13/00

CPC classification number: C11D7/08 ,  C11D7/265 ,  C11D11/0047

Abstract: A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is ascorbic acid or is an organic acid having two or more carboxylic acid groups (e.g., citric acid). The water can be present in about 40 wt. % to about 85 wt. % of the composition, the phosphoric acid can be present in about 0.01 wt. % to about 10 wt. % of the composition, and the organic acid can be present in about 10 wt. % to about 60 wt. % of the composition. The composition can be used for cleaning various surfaces, such as, for example, patterned metal layers and vias by exposing the surfaces to the composition.

公开(公告)号：US06867148B2

公开(公告)日：2005-03-15

申请号：US09858980

申请日：2001-05-16

Applicant: Donald L. Yates ,  Paul A. Morgan

Inventor： Donald L. Yates ,  Paul A. Morgan

IPC: B08B3/08 ,  G03F7/42 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/302

CPC classification number: H01L21/02071 ,  B08B3/08 ,  B08B2203/005 ,  G03F7/423 ,  H01L21/31133

Abstract: Organic acid components are used to increase the solubility of ozone in aqueous solutions for use in removing organic materials, such as polymeric resist and/or post-etch residues, from the surface of an integrated circuit device during fabrication. Each organic acid component is preferably chosen for its metal-passivating effect. Such solutions can have significantly lower corrosion rates when compared to ozonated aqueous solutions using common inorganic acids for ozone solubility enhancement due to the passivating effect of the organic acid component.

Abstract translation: 有机酸组分用于增加臭氧在水溶液中的溶解度，用于在制造期间从集成电路器件的表面去除有机材料，例如聚合物抗蚀剂和/或蚀刻后残留物。 优选选择每种有机酸组分用于其金属钝化作用。 与使用普通无机酸进行臭氧溶解度增强的臭氧化水溶液相比，由于有机酸组分的钝化作用，这种溶液可以具有显着更低的腐蚀速率。

公开(公告)号：US06833084B2

公开(公告)日：2004-12-21

申请号：US09285773

申请日：1999-04-05

Applicant: Garry A. Mercaldi ,  Donald L. Yates

Inventor： Garry A. Mercaldi ,  Donald L. Yates

IPC: C09K1300

CPC classification number: H01L21/32134

Abstract: The present invention provides an etching composition which includes a polyhydric alcohol in combination with two inorganic acids. Preferably the etching composition of the present invention is a mixture of a glycol, nitric acid and hydrofluoric acid, with propylene glycol being preferred. The etching composition of the present invention achieves a selectivity of greater than 70:1, doped material to undoped material. The present invention provides an etching formulation which has increased selectivity of doped polysilicon to undoped polysilicon and provides an efficient integrated circuit fabrication process without requiring time consuming and costly processing modifications to the etching apparatus or production apparatus.

Abstract translation: 本发明提供一种蚀刻组合物，其包含与两种无机酸组合的多元醇。 优选地，本发明的蚀刻组合物是二醇，硝酸和氢氟酸的混合物，优选丙二醇。 本发明的蚀刻组合物实现大于70:1的掺杂材料对未掺杂材料的选择性。 本发明提供了一种蚀刻配方，其具有增加掺杂多晶硅对未掺杂多晶硅的选择性，并且提供了有效的集成电路制造工艺，而不需要对蚀刻设备或生产设备进行耗时且昂贵的处理修改。