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272 条记录 (耗时 0.029 秒)

    Method of fabricating a multi-bit electro-mechanical memory device
    13.
    发明授权
    Method of fabricating a multi-bit electro-mechanical memory device 有权
    制造多位机电存储器件的方法

    公开(公告)号：US07790494B2

    公开(公告)日：2010-09-07

    申请号：US12007819

    申请日：2008-01-16

    申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    IPC分类号： H01L21/00 ,  H01L35/24 ,  H01L51/00 ,  H01L29/792

    CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673

    摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

    摘要翻译： 存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。 位线可以在第一方向上形成在基板上。 第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。 焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。 第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。 第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

    Multi-bit electro-mechanical memory device and method of manufacturing the same
    14.
    发明授权
    Multi-bit electro-mechanical memory device and method of manufacturing the same 失效
    多位机电记忆体装置及其制造方法

    公开(公告)号：US07719068B2

    公开(公告)日：2010-05-18

    申请号：US12002668

    申请日：2007-12-18

    申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

    发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

    IPC分类号： G11C11/50

    CPC分类号： H01L29/788 ,  G11C11/56 ,  G11C23/00

    摘要： There are provided a multi-bit electro-mechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electro-mechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.

    摘要翻译： 提供了能够增强或最大化存储器件的集成度的多位机电存储器件和制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线 并且沿第一方向延伸; 位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。 所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触 字线，并且在第二状态下与字线间隔开。

    Split gate flash memory device having self-aligned control gate and method of manufacturing the same
    15.
    发明授权
    Split gate flash memory device having self-aligned control gate and method of manufacturing the same 有权
    具有自对准控制门的分体式闪存器件及其制造方法

    公开(公告)号：US07652322B2

    公开(公告)日：2010-01-26

    申请号：US12014262

    申请日：2008-01-15

    申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

    发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

    摘要翻译： 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

    TRANSISTOR AND METHOD OF FORMING THE SAME
    17.
    发明申请
    TRANSISTOR AND METHOD OF FORMING THE SAME 有权
    晶体管及其形成方法

    公开(公告)号：US20090170271A1

    公开(公告)日：2009-07-02

    申请号：US12397176

    申请日：2009-03-03

    申请人： Jae-Man YOON ,  Choong-Ho LEE ,  Dong-Gun PARK ,  Chul LEE

    发明人： Jae-Man YOON ,  Choong-Ho LEE ,  Dong-Gun PARK ,  Chul LEE

    IPC分类号： H01L21/426 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

    摘要翻译： 根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。 活性结构包括在源极/漏极区域下形成阻挡区的沟槽。 栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。 可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

    Methods of manufacturing semiconductor memory devices including a vertical channel transistor
    19.
    发明授权
    Methods of manufacturing semiconductor memory devices including a vertical channel transistor 有权
    制造包括垂直沟道晶体管的半导体存储器件的方法

    公开(公告)号：US07531412B2

    公开(公告)日：2009-05-12

    申请号：US11151673

    申请日：2005-06-13

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

    摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

    摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。

    Semiconductor devices having a field effect transistor and methods of fabricating the same
    20.
    发明授权
    Semiconductor devices having a field effect transistor and methods of fabricating the same 有权
    具有场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US07510932B2

    公开(公告)日：2009-03-31

    申请号：US11764751

    申请日：2007-06-18

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78687 ,  Y10S438/933

    摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

    摘要翻译： 提供具有场效应晶体管的半导体器件及其形成方法。 半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。 栅电极优选地跨过器件有源图案，由栅极绝缘层插入。 支撑图案优选地插入在器件活性图案和基底之间。 支撑图案可以设置在栅电极下方。 填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。 填充绝缘图案可以设置在源极/漏极区域下方。 栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。