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    Method and apparatus for making a voice and/or data call over a single analog phone line using a multi-modal DCE
    12.
    发明授权
    Method and apparatus for making a voice and/or data call over a single analog phone line using a multi-modal DCE 失效
    使用多模式DCE通过单个模拟电话线进行语音和/或数据呼叫的方法和装置

    公开(公告)号：US06298121B1

    公开(公告)日：2001-10-02

    申请号：US08910065

    申请日：1997-08-12

    Applicant: Eric Samson ,  Barry O'Mahony ,  Narjala Bhasker

    Inventor： Eric Samson ,  Barry O'Mahony ,  Narjala Bhasker

    IPC: H04M1100

    CPC classification number: H04M11/06

    Abstract: An enhanced micro-controller having multiple operating modes is provided to an otherwise conventional data circuit terminating equipment (DCE). The enhanced micro-controller, responsive to local events as well as local and remote commands, controls the operation of the DCE in one of at least four modes, an idle mode, an analog voice mode, a digital data mode, and a simultaneous voice and data (SVD) mode. As a result of the improved manner in which the micro-controller operates the DCE, users employing the improved DCE may perform voice and data communication using only a single analog-loop telephone line and in a much more user friendly manner.

    Abstract translation: 具有多种操作模式的增强型微控制器被提供给另外常规的数据电路终端设备（DCE）。 增强的微控制器响应于本地事件以及本地和远程命令，以至少四种模式，空闲模式，模拟语音模式，数字数据模式和同时语音中的一种模式控制DCE的操作 和数据（SVD）模式。 作为微控制器操作DCE的改进方式的结果，使用改进的DCE的用户可以仅使用单个模拟回路电话线并以更加用户友好的方式来执行语音和数据通信。

    Dynamic scaling of graphics processor execution resources
    13.
    发明授权
    Dynamic scaling of graphics processor execution resources 有权

    公开(公告)号：US10025367B2

    公开(公告)日：2018-07-17

    申请号：US14463573

    申请日：2014-08-19

    Applicant: Nikos Kaburlasos ,  Eric Samson

    Inventor： Nikos Kaburlasos ,  Eric Samson

    IPC: G06F1/32

    Abstract: In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.

    Efficient Z testing
    15.
    发明授权
    Efficient Z testing 有权
    高效Z测试

    公开(公告)号：US08072451B2

    公开(公告)日：2011-12-06

    申请号：US11023639

    申请日：2004-12-29

    Applicant: Thomas Piazza ,  Eric Samson ,  Nasseh Akaaboune ,  Dinakar Munagala

    Inventor： Thomas Piazza ,  Eric Samson ,  Nasseh Akaaboune ,  Dinakar Munagala

    IPC: G06T15/40 ,  G09G5/02 ,  G09G5/36

    CPC classification number: G06T15/405

    Abstract: Z testing during computer graphics rendering is performed in a manner so as to optimize rendering. The status of a pixel as non-promotable may be tracked using a pixel status array (PSA). Each PSA row may contain bits which correspond to the non-promotable status of pixels. Each row may include five pixels, the first four of which represent the pixels in a subspan. If the row corresponds to a valid subspan, a determination may be made as to whether any pixel in the subspan is represented by a one, indicating that the pixel is non-promotable. This row corresponds to a previous subspan that has been sent down rendering pipeline. If a one is present, then the current subspan may be stalled until the pixels of the previous subspan has gone through color calculation. If, in the row that has just been read, no pixels are represented by a one, then a determination may be made as to whether any pixels in the current subspan are non-promotable. If so, then the corresponding bit in the current PSA row may be set to one. Otherwise, the Z test may be performed on each pixel of the current subspan.

    Abstract translation: 在计算机图形渲染期间的Z测试以优化渲染的方式执行。 可以使用像素状态阵列（PSA）跟踪不可升级的像素的状态。 每个PSA行可以包含对应于像素的不可升级状态的位。 每行可以包括五个像素，其中前四个表示子跨距中的像素。 如果该行对应于有效的子跨度，则可以确定子跨越中的任何像素是否由一个表示，表示该像素是不可升级的。 此行对应于已向下渲染管道发送的先前子跨。 如果存在一个，那么当前的子跨越可能会停顿，直到前一个子跨越的像素经过颜色计算。 如果在刚刚读取的行中没有像素由一个像素表示，则可以确定当前子跨距中的任何像素是否不可升级。 如果是，则当前PSA行中的相应位可以被设置为1。 否则，可以对当前子跨的每个像素执行Z测试。

    Low power display mode
    16.
    发明申请
    Low power display mode 有权
    低功耗显示模式

    公开(公告)号：US20070242076A1

    公开(公告)日：2007-10-18

    申请号：US11322880

    申请日：2006-04-13

    Applicant: Eric Samson ,  Aditya Navale ,  Todd Witter

    Inventor： Eric Samson ,  Aditya Navale ,  Todd Witter

    IPC: G06F13/372

    CPC classification number: G06F3/14 ,  G09G5/006 ,  G09G5/008 ,  G09G5/363 ,  G09G5/39 ,  G09G2330/021

    Abstract: A controller is described that includes wiring to transport notification that a FIFO that holds data to be used to display content on a display has reached a threshold. The controller also includes first control circuitry to turn on a phase locked loop (PLL) circuit to cause logic circuitry within the controller downstream from the PLL to begin to receive a first clock in response to the notification. The logic circuitry is to transport data read from a memory toward the FIFO. The controller also includes second control circuitry to cause the memory to use a second clock provided by the controller in response to the notification.

    Abstract translation: 描述了一种控制器，其包括用于传送通知的连接，即在显示器上保存用于显示内容的数据的FIFO已经达到阈值。 该控制器还包括第一控制电路，用于接通锁相环（PLL）电路，以使PLL内的控制器内的逻辑电路响应该通知开始接收第一时钟。 逻辑电路是将从存储器读取的数据传输到FIFO。 控制器还包括第二控制电路，以使存储器响应于该通知使用由控制器提供的第二时钟。

    Mechanism for self refresh during C0
    18.
    发明申请
    Mechanism for self refresh during C0 有权
    C0期间自刷新机制

    公开(公告)号：US20070157046A1

    公开(公告)日：2007-07-05

    申请号：US11323344

    申请日：2005-12-29

    Applicant: Eric Samson ,  Robert Riesenman

    Inventor： Eric Samson ,  Robert Riesenman

    IPC: G06F1/30

    CPC classification number: G06F13/1636 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061 ,  Y02D10/14

    Abstract: An embodiment may be an apparatus comprising a link coupled with a memory, and circuitry coupled with the link to calculate the amount of memory access idle time, determine if memory access idle time is sufficient to change to a self-refresh state, and change to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Another embodiment may be a method for memory to enter self-refresh comprising calculating the amount of memory access idle time, determining if memory access idle time is sufficient to change to a self-refresh state, and changing to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Various other embodiments systems, methods, machine readable mediums and apparatuses may provide similar functionality to these exemplary embodiments.

    Abstract translation: 实施例可以是包括与存储器耦合的链路的装置，以及与链路耦合的电路，以计算存储器访问空闲时间的量，确定存储器访问空闲时间是否足以改变为自刷新状态，并且改变为 基于存储器访问空闲时间的自刷新状态，而没有来自处理器关于处理器功率状态的显式通知。 另一实施例可以是存储器进入自刷新的方法，包括计算存储器访问空闲时间的量，确定存储器访问空闲时间是否足以改变为自刷新状态，以及基于 存储器访问空闲时间，而没有来自处理器关于处理器功率状态的显式通知。 各种其它实施例系统，方法，机器可读介质和设备可以提供与这些示例性实施例类似的功能。

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