公开(公告)号：US20140149651A1

公开(公告)日：2014-05-29

申请号：US13685991

申请日：2012-11-27

Applicant: Andrew T. Forsyth ,  Ramacharan Sundararaman ,  Eric Sprangle ,  John C. Mejia ,  Douglas M. Carmean ,  Mark C. Davis ,  Edward T. Grochowski ,  Robert D. Cavin

Inventor： Andrew T. Forsyth ,  Ramacharan Sundararaman ,  Eric Sprangle ,  John C. Mejia ,  Douglas M. Carmean ,  Mark C. Davis ,  Edward T. Grochowski ,  Robert D. Cavin

IPC: G06F12/08

CPC classification number: G06F12/126 ,  G06F12/123 ,  Y02D10/13

Abstract: In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括解码逻辑，用于接收和解码第一存储器访问指令以将数据存储在具有第一级的替换状态指示符的高速缓冲存储器中，并将解码的第一存储器访问指令发送到控制逻辑。 反过来，控制逻辑是以第一组高速缓冲存储器的第一种方式存储数据，并且响应于解码的第一存储器访问指令将第一级的替换状态指示符存储在第一方式的元数据字段中 。 描述和要求保护其他实施例。

公开(公告)号：US20140130058A1

公开(公告)日：2014-05-08

申请号：US14154517

申请日：2014-01-14

Applicant: Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06F9/50

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程。

公开(公告)号：US08681173B2

公开(公告)日：2014-03-25

申请号：US11967492

申请日：2007-12-31

Applicant: Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Tom Forsyth ,  Michael Abrash

Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Tom Forsyth ,  Michael Abrash

IPC: G09G5/00

CPC classification number: G06T1/20 ,  G06F9/3867

Abstract: A system and method for generating a single compressed vector including two or more predetermined attribute values. For each of a plurality of data points such as pixels, if a first and a second attribute values of the data point are equal to a first and a second, respectively, of the two or more predetermined attribute values, the compressed vector is used to operate on the data point. Other embodiments are described and claimed.

Abstract translation: 一种用于生成包括两个或多个预定属性值的单个压缩向量的系统和方法。 对于诸如像素的多个数据点中的每一个，如果数据点的第一和第二属性值分别等于两个或更多个预定属性值的第一和第二属性值，则使用压缩向量 在数据点上操作。 描述和要求保护其他实施例。

公开(公告)号：US08667250B2

公开(公告)日：2014-03-04

申请号：US11964631

申请日：2007-12-26

Applicant: Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

Inventor： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

IPC: G06F9/312

CPC classification number: G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

Abstract translation: 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。

公开(公告)号：US20130318374A1

公开(公告)日：2013-11-28

申请号：US13954980

申请日：2013-07-31

Applicant: Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06F1/32

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system

公开(公告)号：US20130246719A1

公开(公告)日：2013-09-19

申请号：US13785544

申请日：2013-03-05

Applicant: ERIC SPRANGLE

Inventor： ERIC SPRANGLE

IPC: G06F3/06

CPC classification number: G06T1/20 ,  G06F3/0644 ,  G06F9/30043 ,  G06F9/3867 ,  G06F9/5016

Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.

公开(公告)号：US20130232318A1

公开(公告)日：2013-09-05

申请号：US13844111

申请日：2013-03-15

Applicant: Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

Inventor： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

IPC: G06F9/30

CPC classification number: G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

公开(公告)号：US08065488B2

公开(公告)日：2011-11-22

申请号：US12908183

申请日：2010-10-20

Applicant: Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin

Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin

IPC: G06F12/12

CPC classification number: G06F12/127 ,  G06F12/0862 ,  G06F12/124 ,  G06F2212/6028

Abstract: A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.

Abstract translation: 本文描述了用于有效地高速缓存流和非流数据的方法和装置。 诸如编译器的软件识别最后使用的流指令/操作，这些指令/操作是用于访问多个指令或一定时间量的最后指令/操作来访问流数据。 作为执行对最后使用指令/操作的高速缓存线的访问的结果，将高速缓存行更新为不再需要的流数据（SDN）状态。 当控制逻辑要确定要替换的高速缓存行时，修改的最近最少使用（LRU）算法被偏置以首先选择SDN状态行来替换不再需要的流数据。

公开(公告)号：US20100332801A1

公开(公告)日：2010-12-30

申请号：US12492652

申请日：2009-06-26

Applicant: Joshua B. Fryman ,  Edward T. Grochowski ,  Toni Juan ,  Andrew Thomas Forsyth ,  John Mejia ,  Ramacharan Sundararaman ,  Eric Sprangle ,  Roger Espasa ,  Ravi Rajwar

Inventor： Joshua B. Fryman ,  Edward T. Grochowski ,  Toni Juan ,  Andrew Thomas Forsyth ,  John Mejia ,  Ramacharan Sundararaman ,  Eric Sprangle ,  Roger Espasa ,  Ravi Rajwar

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0817

Abstract: In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括在处理器核心中接收用于解码的指令，并且基于是否预测争用来动态地处理具有多种行为之一的指令。 如果没有预测到竞争，则在核心中执行指令，并且如果竞争是预测与指令相关联的数据被编组并发送到所选择的远程代理执行。 描述和要求保护其他实施例。

公开(公告)号：US06721866B2

公开(公告)日：2004-04-13

申请号：US10029367

申请日：2001-12-21

Applicant: Patrice Roussel ,  Eric Sprangle ,  Glenn J. Hinton

Inventor： Patrice Roussel ,  Eric Sprangle ,  Glenn J. Hinton

IPC: G06F1204

CPC classification number: G06F9/30043

Abstract: A method of obtaining an operand from a memory device includes reading a first operand from a first location in a memory device, the first operand including part of the operand specified by an instruction, shifting the first operand by a first shift amount, reading a second data operand from the memory device, the second operand having part of the operand specified by the instruction, shifting the second operand by a second shift amount, and combining the first shifted data entry and the second shifted data entry to produce an aligned operand, wherein shifting the first operand and shifting the second operand is performed by a shifter also used for floating point functions.

Abstract translation: 从存储装置获取操作数的方法包括从存储装置中的第一位置读取第一操作数，第一操作数包括由指令指定的操作数的一部分，将第一操作数移位第一移位量，读第二操作数 来自存储器件的数据操作数，第二操作数具有由指令指定的操作数的一部分，将第二操作数移位第二移位量，并组合第一移位数据条目和第二移位数据条目以产生对准的操作数，其中 移动第一操作数并移动第二操作数由也用于浮点函数的移位器执行。