公开(公告)号：US06173366B2

公开(公告)日：2001-01-09

申请号：US08759044

申请日：1996-12-02

Applicant: John S. Thayer ,  John G. Favor ,  Frederick D. Weber

Inventor： John S. Thayer ,  John G. Favor ,  Frederick D. Weber

IPC: G06F1204

CPC classification number: G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F12/0875 ,  H04N19/42 ,  H04N19/61

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

公开(公告)号：US6154831A

公开(公告)日：2000-11-28

申请号：US296356

申请日：1999-04-22

Applicant: John S. Thayer ,  Gary W. Thome ,  John G. Favor ,  Frederick D. Weber

Inventor： John S. Thayer ,  Gary W. Thome ,  John G. Favor ,  Frederick D. Weber

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F9/3885 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3824

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The MEU may include a plurality of ALUs, registers partitioned into slots, and a decode unit for decoding an instruction specifying operands from any slot from one register and from a fixed slot of another register as well as different operations to be performed by the ALUs on the operands.

Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 MEU可以包括多个ALU，被划分成时隙的寄存器，以及解码单元，用于对来自一个寄存器和另一个寄存器的固定时隙的任何时隙指定操作数的指令进行解码，以及由ALU执行的不同操作 操作数。

公开(公告)号：US6141673A

公开(公告)日：2000-10-31

申请号：US318671

申请日：1999-05-25

Applicant: John S. Thayer ,  John Gregory Favor ,  Frederick D. Weber

Inventor： John S. Thayer ,  John Gregory Favor ,  Frederick D. Weber

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F17/14

CPC classification number: G06F9/30072 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地中央处理单元（CPU）总线耦合到常规处理器。 MEU采用向量寄存器，向量算术逻辑单元（ALU）和操作数路由单元（ORU），以尽可能少的指令周期执行最大数量的多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

公开(公告)号：US6093213A

公开(公告)日：2000-07-25

申请号：US649982

申请日：1996-05-16

Applicant: John G. Favor ,  Frederick D. Weber

Inventor： John G. Favor ,  Frederick D. Weber

IPC: G06F7/74 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/445 ,  G06F9/455 ,  G06F9/48 ,  G06F9/44

CPC classification number: G06F7/74 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/445 ,  G06F9/45533 ,  G06F9/4812

Abstract: A system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is "soft" and freely defined. A system management interrupt (SMI) pin is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.

公开(公告)号：US5960461A

公开(公告)日：1999-09-28

申请号：US403308

申请日：1995-03-14

Applicant: Steven J. Frank ,  Henry Burkhardt, III ,  Linda O. Lee ,  Nathan Goodman ,  Benson I. Margulies ,  Frederick D. Weber

Inventor： Steven J. Frank ,  Henry Burkhardt, III ,  Linda O. Lee ,  Nathan Goodman ,  Benson I. Margulies ,  Frederick D. Weber

IPC: G06F15/177 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F11/00 ,  G06F11/07 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  H04L12/46 ,  H04L12/56 ,  G06F12/14

CPC classification number: G06F9/5016 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0766 ,  G06F11/0772 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0833 ,  G06F12/10 ,  G06F12/1018 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/468 ,  G06F9/52 ,  H04L12/4637 ,  H04L45/04 ,  G06F12/126 ,  G06F2212/272

Abstract: A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

Abstract translation: 多处理器数字数据处理系统包括以环的分层布置的多个处理单元。 系统选择性地分配存储并且响应于由单元产生的访问请求而将独占数据副本从单元移动到单元。 采用路由元素来选择性地广播环上的数据访问请求，更新和传送。

公开(公告)号：US07007300B1

公开(公告)日：2006-02-28

申请号：US09870890

申请日：2001-05-30

Applicant: Frederick D. Weber ,  Dale E. Gulick ,  Geoffrey S. Strongin

Inventor： Frederick D. Weber ,  Dale E. Gulick ,  Geoffrey S. Strongin

IPC: H04K1/00 ,  H04L9/32 ,  H04N7/16

Abstract: Methods for securing booting a personal computer system. One method includes establishing a secret between two or more devices and securing the secret in each of the two or more devices. Another method includes processing BIOS code instructions and accessing security hardware. The method also includes accessing a first device, locking the security hardware, and calling boot code. Another method includes reading a secret from a first location, storing the secret in a secure location different from the first location, and locking the first location. Another method includes requesting authentication for a device, receiving authentication for the device, and setting a timer associated with the device. Another method includes requesting authentication for a device, failing authentication for the device, and preventing access to the device upon failing authentication for the device.

Abstract translation: 用于确保启动个人计算机系统的方法。 一种方法包括在两个或更多个设备之间建立秘密，并且在两个或更多个设备中的每一个中确保秘密。 另一种方法包括处理BIOS代码指令和访问安全硬件。 该方法还包括访问第一设备，锁定安全硬件和调用引导代码。 另一种方法包括从第一位置读取秘密，将秘密存储在与第一位置不同的安全位置，并锁定第一位置。 另一种方法包括请求对设备的认证，接收设备的认证，以及设置与设备相关联的定时器。 另一种方法包括请求设备认证，设备认证失败，以及在设备认证失败时阻止对设备的访问。

公开(公告)号：US06446189B1

公开(公告)日：2002-09-03

申请号：US09323321

申请日：1999-06-01

Applicant: Gerald D. Zuraski, Jr. ,  Frederick D. Weber ,  William A. Hughes ,  William K. Lewchuk ,  Scott A. White ,  Michael T. Clark

Inventor： Gerald D. Zuraski, Jr. ,  Frederick D. Weber ,  William A. Hughes ,  William K. Lewchuk ,  Scott A. White ,  Michael T. Clark

IPC: G06F1200

CPC classification number: G06F12/1054

Abstract: A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e.g., a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU. The BIU includes address translation circuitry, a multiplexer, and gating logic, and returns the physical address corresponding to the linear address to the cache unit. The cache unit stores the physical address and the linear address within the TLB. The processor may also include a programmable control register and a microexecution unit. Upon detecting a change in state of an external masking signal, the microexecution unit may flush the contents of the TLB and modify a masking bit within the control register to reflect a new state of the masking signal.

Abstract translation: 呈现包括耦合到总线接口单元（BIU）的高速缓存单元的处理器。 地址信号选择和屏蔽功能由BIU内的电路而不是在高速缓存单元内执行，而由BIU生成的物理地址存储在TLB内。 结果，从高速缓存单元内的临界速度路径消除了地址信号选择和屏蔽电路（例如，多路复用器和门控逻辑），从而允许高速缓存单元的操作速度增加。 高速缓存单元存储数据项，并产生与所接收的线性地址对应的数据项。 缓存单元内的翻译后备缓冲器（TLB）存储多个线性地址和对应的物理地址。 当在TLB内没有找到与接收到的线性地址对应的物理地址时，高速缓存单元将线性地址传递给BIU。 BIU包括地址转换电路，多路复用器和门控逻辑，并将对应于线性地址的物理地址返回到高速缓存单元。 高速缓存单元存储TLB内的物理地址和线性地址。 处理器还可以包括可编程控制寄存器和微执行单元。 在检测到外部屏蔽信号的状态变化时，微执行单元可以刷新TLB的内容并修改控制寄存器内的屏蔽位以反映掩蔽信号的新状态。

公开(公告)号：US06298438B1

公开(公告)日：2001-10-02

申请号：US09303513

申请日：1999-05-03

Applicant: John S. Thayer ,  John G. Favor ,  Frederick D. Weber

Inventor： John S. Thayer ,  John G. Favor ,  Frederick D. Weber

IPC: G06F738

CPC classification number: G06F9/30072 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

公开(公告)号：US6105129A

公开(公告)日：2000-08-15

申请号：US25233

申请日：1998-02-18

Applicant: Stephan G. Meier ,  Norbert Juffa ,  Michael D. Achenbach ,  Frederick D. Weber

Inventor： Stephan G. Meier ,  Norbert Juffa ,  Michael D. Achenbach ,  Frederick D. Weber

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/302

CPC classification number: G06F9/30181 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30152 ,  G06F9/30185 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3861

Abstract: A microprocessor includes one or more registers which are architecturally defined to be used for at least two data formats. In one embodiment, the registers are the floating point registers defined in the x86 architecture, and the data formats are the floating point data format and the multimedia data format. The registers actually implemented by the microprocessor for the floating point registers use an internal format for floating point data. Part of the internal format is a classification field which classifies the floating point data in the extended precision defined by the x86 microprocessor architecture. Additionally, a classification field encoding is reserved for multimedia data. As the microprocessor begins execution of each multimedia instruction, the classification information of the source operands is examined to determine if the data is either in the multimedia class, or in a floating point class in which the significand portion of the register is the same as the corresponding significand in extended precision. If so, the multimedia instruction executes normally. If not, the multimedia instruction is faulted. Similarly, as the microprocessor begins execution of each floating point instruction, the classification information of the source operands is examined. If the data is classified as multimedia, the floating point instruction is faulted. A microcode routine is used to reformat the data stored in at least the source registers of the faulting instruction into a format useable by the faulting instruction. Subsequently, the faulting instruction is re-executed.

Abstract translation: 微处理器包括一个或多个寄存器，其被架构地定义为用于至少两种数据格式。 在一个实施例中，寄存器是在x86架构中定义的浮点寄存器，数据格式是浮点数据格式和多媒体数据格式。 微处理器为浮点寄存器实际实现的寄存器使用浮点数据的内部格式。 内部格式的一部分是分类字段，它以由x86微处理器架构定义的扩展精度对浮点数据进行分类。 此外，分类字段编码被保留用于多媒体数据。 当微处理器开始执行每个多媒体指令时，检查源操作数的分类信息以确定数据是在多媒体类中还是在浮点类中，其中寄存器的有效部分与 相应的显着性在扩展精度。 如果是这样，多媒体指令正常执行。 如果不是，则多媒体指令发生故障。 类似地，当微处理器开始执行每个浮点指令时，检查源操作数的分类信息。 如果数据被分类为多媒体，则浮点指令发生故障。 微码程序用于将存储在故障指令的至少源寄存器中的数据重新格式化为故障指令可使用的格式。 随后，重新执行故障指令。

公开(公告)号：US5822578A

公开(公告)日：1998-10-13

申请号：US461166

申请日：1995-06-05

Applicant: Steven Frank ,  Henry Burkhardt, III ,  Frederick D. Weber ,  Linda Q. Lee ,  John A. Roskosz ,  Brett D. Byers ,  Peter C. Schnorr ,  David I. Epstein

Inventor： Steven Frank ,  Henry Burkhardt, III ,  Frederick D. Weber ,  Linda Q. Lee ,  John A. Roskosz ,  Brett D. Byers ,  Peter C. Schnorr ,  David I. Epstein

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F11/00 ,  G06F11/07 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  H04L12/46 ,  H04L12/56 ,  G06F9/00

CPC classification number: G06F9/5016 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0772 ,  G06F12/0811 ,  G06F12/10 ,  G06F9/3005 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/468 ,  G06F9/52 ,  H04L12/4637 ,  H04L45/04 ,  G06F12/126 ,  G06F2212/272

Abstract: Digital multiprocessor methods and apparatus comprise a plurality of processors, including a first processor for normally processing an instruction stream including instructions from a first instruction source. At least one of the processors can transmit inserted-instructions to the first processor. Inserted-instructions are executed by the first processor in the same manner as, and without affecting the sequence of, instructions from the first instruction source. The first instruction source can be a memory element, including an instruction cache element for storing digital values representative of instructions and program steps, or an execution unit (CEU) which asserts signals to the instruction cache element to cause instructions to be transmitted to the CEU. The processors include input/output (I/O) processors having direct memory access (DMA) insert elements, which respond to a peripheral device to generate DMA inserted-instructions. These DMA inserted-instructions are executable by the first processing element in the same manner as, and without affecting processing sequence of, the instructions from the first instruction source.

Abstract translation: 数字多处理器方法和装置包括多个处理器，包括用于正常处理包括来自第一指令源的指令的指令流的第一处理器。 至少一个处理器可以将插入的指令发送到第一处理器。 插入指令以与第一指令源相同的方式由第一处理器执行，而不影响来自第一指令源的指令序列。 第一指令源可以是存储元件，包括用于存储表示指令和程序步骤的数字值的指令高速缓存元件，或者执行单元（CEU），其向指令高速缓存元件发出信号以使指令被发送到CEU 。 处理器包括具有直接存储器访问（DMA）插入元件的输入/输出（I / O）处理器，其响应于外围设备以产生DMA插入指令。 这些DMA插入指令可以由第一处理元件以与来自第一指令源的指令的处理顺序相同的方式执行，并且不影响来自第一指令源的指令的处理顺序。