公开(公告)号：US20110248383A1

公开(公告)日：2011-10-13

申请号：US12757612

申请日：2010-04-09

Applicant: Liping REN ,  Hsiao-Chin TUAN ,  Dah-Chuen HO

Inventor： Liping REN ,  Hsiao-Chin TUAN ,  Dah-Chuen HO

IPC: H01L27/06 ,  H01L23/60

CPC classification number: H01L27/0259 ,  H01L2224/16225 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An electrostatic discharge (ESD) protection circuit includes at least one bipolar transistor. At least one isolation structure is disposed in a substrate. The at least one isolation structure is configured to electrically isolate two terminals of the at least one bipolar transistor. At least one diode is electrically coupled with the at least one bipolar transistor, wherein a junction interface of the at least one diode is disposed adjacent the at least one isolation structure.

Abstract translation: 静电放电（ESD）保护电路包括至少一个双极晶体管。 在衬底中设置至少一个隔离结构。 所述至少一个隔离结构被配置为电隔离所述至少一个双极晶体管的两个端子。 至少一个二极管与所述至少一个双极晶体管电耦合，其中所述至少一个二极管的结界面邻近所述至少一个隔离结构设置。

公开(公告)号：US20110163376A1

公开(公告)日：2011-07-07

申请号：US12652294

申请日：2010-01-05

Applicant: Chih-Chang CHENG ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

Inventor： Chih-Chang CHENG ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L24/16 ,  H01L24/48 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.

Abstract translation: 高压（HV）器件包括设置在衬底中的第一掺杂剂类型的阱区。 第二掺杂剂类型的第一阱区域设置在第一掺杂剂类型的阱区域中。 隔离结构至少部分地设置在第一掺杂剂类型的阱区中。 第一栅电极设置在隔离结构和第二掺杂剂类型的第一阱区之上。 第二掺杂剂类型的第二阱区设置在第一掺杂剂类型的阱区中。 第二掺杂剂类型的第二阱区域与第二掺杂剂类型的第一阱区域间隔开。 第二栅电极设置在第二掺杂剂类型的第一阱区域和第二掺杂剂类型的第二阱区域之间和之上。

公开(公告)号：US20110156217A1

公开(公告)日：2011-06-30

申请号：US12651322

申请日：2009-12-31

Applicant: Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

Inventor： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

IPC: H01L23/58 ,  H01L21/78

CPC classification number: H01L29/66712 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.

Abstract translation: 提供一种形成用于支撑和处理包含形成在其前表面上的垂直FET的半导体晶片的支撑结构的方法。 在一个实施例中，提供具有前表面和后表面的半导体晶片，其中前表面包括由切割线分开的一个或多个裸片。 将晶片减薄至预定厚度。 多个图案化的金属特征形成在薄的后表面上以提供对晶片的支撑，其中多个图案化的金属特征中的每一个基本上覆盖一个管芯，使切割线基本上不被覆盖。 然后，晶片沿着切割线切割，以分离一个或多个模具用于稍后的芯片封装。

公开(公告)号：US06221558B1

公开(公告)日：2001-04-24

申请号：US09054350

申请日：1998-04-02

Applicant: Liang-Gi Yao ,  John Chin-Hsiang Lin ,  Hua-Tai Lin ,  Erik S. Jeng ,  Hsiao-Chin Tuan

Inventor： Liang-Gi Yao ,  John Chin-Hsiang Lin ,  Hua-Tai Lin ,  Erik S. Jeng ,  Hsiao-Chin Tuan

IPC: G03F711

CPC classification number: H01L21/0276 ,  G03F7/091 ,  H01L21/32139

Abstract: The present invention provides an anti-reflection films for lithographic application on polysilicon containing substrate. A structure for improving lithography patterning in an integrated circuit comprises a polysilicon layer, a diaphanous layer located above the polysilicon layer, an anti-reflection layer located above the diaphanous layer, and then a photoresist layer located above the anti-reflection layer for patterning the integrated circuit pattern. The anti-reflection layer is preferably oxynitride.

Abstract translation: 本发明提供了一种用于在含多晶硅的衬底上进行光刻的抗反射膜。 用于改进集成电路中的光刻图案化的结构包括多晶硅层，位于多晶硅层上方的透明层，位于透光层上方的抗反射层，然后位于抗反射层上方的用于图案化的抗蚀剂层 集成电路图案。 抗反射层优选为氮氧化合物。

公开(公告)号：US5395784A

公开(公告)日：1995-03-07

申请号：US46777

申请日：1993-04-14

Applicant: Chih-Yuan Lu ,  Nicky C. Lu ,  Hsiao-Chin Tuan

Inventor： Chih-Yuan Lu ,  Nicky C. Lu ,  Hsiao-Chin Tuan

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/10861 ,  H01L27/10808

Abstract: A method for making a DRAM MOSFET integrated circuit and resulting device having low leakage and long retention time in a semiconductor wafer is described. A pattern of gate dielectric and gate electrode structures is provided over the semiconductor wafer having a first conductivity imparting dopant in the cell array region and the peripheral circuits region of the integrated circuit. The pattern of gate dielectric and gate electrode structures as a mask for ion implantation to form lightly doped regions of a second and opposite conductivity imparting dopant in the semiconductor wafer wherein certain of the lightly doped regions within the cell array region are to be bit line regions and capacitor node regions. A capacitor is formed within the cell array region. An interlevel dielectric insulating layer is formed over the surface of the structure. A highly doped bit line contact is formed to the bit line regions. The structure is heated to anneal out the ion implantation damage in the lightly doped regions caused by the ion implantation into the lightly doped regions and to cause outdiffusion from the doped bit line contact layer to form a highly doped bit line contact within certain of the lightly doped regions wherein the low leakage and long retention time are the resulting circuit characteristics.

Abstract translation: 描述了制造DRAM MOSFET集成电路的方法以及在半导体晶片中具有低泄漏和长保留时间的所得器件。 栅电介质和栅极电极结构的图案设置在半导体晶片上，该半导体晶片在单元阵列区域和集成电路的外围电路区域中具有赋予第一导电性的掺杂剂。 作为用于离子注入的掩模的栅极电介质和栅电极结构的图案，以在半导体晶片中形成第二相反导电赋予掺杂剂的轻掺杂区域，其中单元阵列区域内的某些轻掺杂区域将是位线区域 和电容器节点区域。 在电池阵列区域内形成电容器。 在结构的表面上形成层间绝缘层。 高位掺杂的位线接触形成在位线区域。 该结构被加热以退出在由轻离子注入到轻掺杂区域中引起的轻掺杂区域中的离子注入损伤，并引起来自掺杂位线接触层的扩散扩散，从而在轻微掺杂区域内形成高度掺杂的位线接触 掺杂区域，其中低泄漏和长保留时间是得到的电路特性。

公开(公告)号：US5338750A

公开(公告)日：1994-08-16

申请号：US982708

申请日：1992-11-27

Applicant: Hsiao-Chin Tuan ,  Hu H. Chao

Inventor： Hsiao-Chin Tuan ,  Hu H. Chao

IPC: H01L21/32 ,  H01L21/76

CPC classification number: H01L21/32

Abstract: A method of forming a silicon oxide isolation region on the surface of a silicon wafer consisting of a thin layer of silicon oxide on the wafer, a layer of impurity-doped polysilicon, and a layer of silicon nitride. The oxidation mask is formed by patterning the silicon nitride layer and at least a portion of the doped polysilicon layer. The silicon oxide field isolation region is formed by subjecting the structure to a thermal oxidation ambient. The oxidation mask is removed in one continuous etching step using a single etchant, such as phosphoric acid which etches the silicon nitride and polysilicon layers at substantially the same rate to complete the formation of the isolation region without pitting the monocrystalline substrate.

Abstract translation: 在硅晶片的表面上形成氧化硅隔离区的方法，所述硅晶片由晶圆上的薄氧化硅组成，杂质掺杂多晶硅层和氮化硅层组成。 通过图案化氮化硅层和掺杂多晶硅层的至少一部分来形成氧化掩模。 氧化硅场隔离区域通过使结构体经受热氧化环境而形成。 在一个连续蚀刻步骤中使用单一蚀刻剂除去氧化掩模，所述蚀刻剂例如以基本上相同的速率蚀刻氮化硅和多晶硅层的磷酸，以完成隔离区的形成，而不会点蚀单晶衬底。

公开(公告)号：US5196367A

公开(公告)日：1993-03-23

申请号：US697190

申请日：1991-05-08

Applicant: Chih-Yuan Lu ,  Hsiao-Chin Tuan

Inventor： Chih-Yuan Lu ,  Hsiao-Chin Tuan

IPC: H01L21/762

CPC classification number: H01L21/76216 ,  Y10S148/117

Abstract: A method for fabricating semiconductor devices having field oxide isolation with channel stop is described which overcomes the encroachment problems of the prior art. A semiconductor substrate is provided. A multilayer oxidation masking structure of a silicon oxide layer, a polycrystalline silicon layer and a silicon nitride layer is formed. The multilayer oxidation mask is patterned by removing the silicon nitride layer and a portion of the polycrystalline silicon layer in the areas designated to have field oxide isolation grown therein. A sidewall insulator structure is formed on the exposed sidewalls of the patterned oxidation mask. Impurities are implanted into the area designated to have field oxide isolation to form the channel stop. The sidewall insulator structure is removed. The field oxide insulator structure is grown by subjecting the structure to oxidation whereby the channel stop is confined under the field oxide isolation and not encroaching the planned device regions.

Abstract translation: 描述了一种用于制造具有通道停止的场氧化物隔离的半导体器件的方法，其克服了现有技术的侵入问题。 提供半导体衬底。 形成氧化硅层，多晶硅层和氮化硅层的多层氧化掩模结构。 通过在指定为在其中生长的场氧化物隔离的区域中去除氮化硅层和多晶硅层的一部分来图案化多层氧化掩模。 在图案化氧化掩模的暴露的侧壁上形成侧壁绝缘体结构。 将杂质植入指定为具有场氧化物隔离的区域以形成通道停止。 去除侧壁绝缘体结构。 通过对结构进行氧化来生长场氧化物绝缘体结构，由此在场氧化物隔离下限制通道停止，而不会侵蚀计划的器件区域。

公开(公告)号：US10014291B2

公开(公告)日：2018-07-03

申请号：US13760496

申请日：2013-02-06

Applicant: Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai ,  Hsiao-Chin Tuan ,  Alex Kalnitsky

Inventor： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai ,  Hsiao-Chin Tuan ,  Alex Kalnitsky

IPC: H01L29/15 ,  H01L27/06 ,  H01L21/8258 ,  H01L27/085 ,  H01L21/265

CPC classification number: H01L27/0617 ,  H01L21/26506 ,  H01L21/8258 ,  H01L27/085 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.

公开(公告)号：US09698044B2

公开(公告)日：2017-07-04

申请号：US13308957

申请日：2011-12-01

Applicant: Alex Kalnitsky ,  Chih-Wen Yao ,  Jun Cai ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

Inventor： Alex Kalnitsky ,  Chih-Wen Yao ,  Jun Cai ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/092 ,  H01L21/265 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/76237 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/76216 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/82385 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/1087

Abstract: A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.

公开(公告)号：US08497551B2

公开(公告)日：2013-07-30

申请号：US12792025

申请日：2010-06-02

Applicant: Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Kuo-Ming Wu ,  Wei Tsung Huang

Inventor： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Kuo-Ming Wu ,  Wei Tsung Huang

IPC: H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased.

Abstract translation: 上述用于产生沟槽MOSFET的工艺方法和结构使得能够形成自对准触点，以允许减小沟槽MOSFET的间距尺寸。 通过蚀刻暴露的硅区域而不使用光刻掩模和对准来形成自对准触点。 结果，可以节省对准的余量，并且可以减小间距尺寸。