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公开(公告)号：US08558611B2
公开(公告)日：2013-10-15
申请号：US13372709
申请日：2012-02-14
IPC分类号： H03F3/68
CPC分类号： H03F3/195 , H03F3/45197 , H03F2203/45458 , H03F2203/45494 , H03F2203/45512 , H03F2203/45528 , H03F2203/45631 , H03F2203/45634 , H03F2203/45702 , H03F2203/45726
摘要： Analog peaking amplifiers with enhanced peaking capability are provided. For example, a peaking amplifier circuit includes an input node, output node, a feedback node, a first input amplifier having an input connected to the input node and an output connected to the feedback node, a second input amplifier having an input connected to the input node, a coupling capacitor connected between an output of the second input amplifier and the feedback node, a forward-path gain amplifier having an input connected to the feedback node and an output connected to the output node, and a feedback circuit having an input coupled to the output node and an output connected to the feedback node. A peaking response of the peaking amplifier circuit is realized by capacitively coupling the output of the second input amplifier to the feedback node to suppress negative feedback and increase the peaking gain at higher frequencies.
摘要翻译： 提供了具有增强峰值能力的模拟峰值放大器。 例如，峰值放大器电路包括输入节点，输出节点，反馈节点，具有连接到输入节点的输入端的第一输入放大器和连接到反馈节点的输出端，第二输入放大器，其输入端连接到 输入节点，连接在第二输入放大器的输出端和反馈节点之间的耦合电容器，具有连接到反馈节点的输入端和连接到输出节点的输出端的前向增益放大器，以及具有输入端的反馈电路 耦合到输出节点和连接到反馈节点的输出。 通过将第二输入放大器的输出电容耦合到反馈节点来实现峰化放大器电路的峰值响应，以抑制负反馈并增加在较高频率下的峰值增益。
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公开(公告)号：US08547732B2
公开(公告)日：2013-10-01
申请号：US13346847
申请日：2012-01-10
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C8/14 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/44 , H01L27/18 , H01L27/222
摘要： In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
摘要翻译： 在一个实施例中，本发明是混合超导磁存储器单元和阵列。 存储单元的一个实施例包括磁阻元件和与磁阻元件平行布线的至少一个超导元件。 在另一实施例中，所公开的配置的存储器单元被布置成形成存储器阵列。
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公开(公告)号：US20130207722A1
公开(公告)日：2013-08-15
申请号：US13372709
申请日：2012-02-14
IPC分类号： H03F3/45
CPC分类号： H03F3/195 , H03F3/45197 , H03F2203/45458 , H03F2203/45494 , H03F2203/45512 , H03F2203/45528 , H03F2203/45631 , H03F2203/45634 , H03F2203/45702 , H03F2203/45726
摘要： Analog peaking amplifiers with enhanced peaking capability are provided. For example, a peaking amplifier circuit includes an input node, output node, a feedback node, a first input amplifier having an input connected to the input node and an output connected to the feedback node, a second input amplifier having an input connected to the input node, a coupling capacitor connected between an output of the second input amplifier and the feedback node, a forward-path gain amplifier having an input connected to the feedback node and an output connected to the output node, and a feedback circuit having an input coupled to the output node and an output connected to the feedback node. A peaking response of the peaking amplifier circuit is realized by capacitively coupling the output of the second input amplifier to the feedback node to suppress negative feedback and increase the peaking gain at higher frequencies.
摘要翻译： 提供了具有增强峰值能力的模拟峰值放大器。 例如，峰值放大器电路包括输入节点，输出节点，反馈节点，具有连接到输入节点的输入端的第一输入放大器和连接到反馈节点的输出端，第二输入放大器，其输入端连接到 输入节点，连接在第二输入放大器的输出端和反馈节点之间的耦合电容器，具有连接到反馈节点的输入端和连接到输出节点的输出端的前向增益放大器，以及具有输入端的反馈电路 耦合到输出节点和连接到反馈节点的输出。 通过将第二输入放大器的输出电容耦合到反馈节点来实现峰化放大器电路的峰值响应，以抑制负反馈并增加在较高频率下的峰值增益。
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公开(公告)号：US20130207702A1
公开(公告)日：2013-08-15
申请号：US13534241
申请日：2012-06-27
IPC分类号： H03K3/84
CPC分类号： H03K17/005 , H03K3/017 , H03K5/1565
摘要： Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.
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15.发明申请公开(公告)号：US20120314757A1
公开(公告)日：2012-12-13
申请号：US13590913
申请日：2012-08-21
申请人： John F. Bulzacchelli , Byungsub Kim
发明人： John F. Bulzacchelli , Byungsub Kim
CPC分类号： H03K3/35613 , H03K3/012 , H03K3/356139 , H04L25/03006 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L2025/0349
摘要： A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.
摘要翻译： 1 / n速率判决反馈均衡器（DFE）和方法包括多个分支。 每个分支包括一个加法电路，其被配置为向接收到的输入添加反馈信号，以及锁存器，被配置为根据时钟信号接收加法电路的输出。 反馈电路包括被配置为接收每个分支的输出作为输入的多路复用器，所述多路复用器具有时钟选择输入并且被配置为多路复用每个分支的输出以组合全速比特序列，以及被配置为提供消除 来自接收输入的符号间干扰（ISI）提供给每个分支的夏季电路。
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公开(公告)号：US08183948B2
公开(公告)日：2012-05-22
申请号：US12702798
申请日：2010-02-09
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译： 振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。 两个LC坦克被嵌套和切换。 通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。
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17.发明申请公开(公告)号：US20110309888A1
公开(公告)日：2011-12-22
申请号：US12818790
申请日：2010-06-18
申请人： John F. BULZACCHELLI , Zeynep Toprak DENIZ , Daniel Joseph FRIEDMAN , Shahrzad NARAGHI , Alexander V. RYLYAKOV
发明人： John F. BULZACCHELLI , Zeynep Toprak DENIZ , Daniel Joseph FRIEDMAN , Shahrzad NARAGHI , Alexander V. RYLYAKOV
IPC分类号： H03L5/00
CPC分类号： H03L7/0995 , H03M1/0612 , H03M1/14 , H03M1/502 , H03M1/60
摘要： Apparatuses and methods are provided relating to a voltage controlled oscillator (VCO) based on current starved inverting delay stages; wherein in each stage a PMOS transistor as header and an NMOS transistor as footer are used with their gate-to-source voltages always equal to analog control voltage. The analog control voltage is also used as the supply voltage of the oscillator. An exemplary apparatus includes a VCO of n stages, where n is an odd number and where each stage includes a current starved inverter where the analog control voltage is also used as the supply voltage of each delay stage.
摘要翻译： 提供了关于基于当前饥饿的反相延迟级的压控振荡器（VCO）的装置和方法; 其中在每个阶段中，使用PMOS晶体管作为集管和作为栅极的NMOS晶体管，其栅极至源极电压总是等于模拟控制电压。 模拟控制电压也用作振荡器的电源电压。 示例性装置包括n级的VCO，其中n是奇数，并且其中每级包括当前饥饿逆变器，其中模拟控制电压也用作每个延迟级的电源电压。
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公开(公告)号：US20110063038A1
公开(公告)日：2011-03-17
申请号：US12702798
申请日：2010-02-09
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译： 振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。 两个LC坦克被嵌套和切换。 通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。
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公开(公告)号：US07822114B2
公开(公告)日：2010-10-26
申请号：US11761586
申请日：2007-06-12
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/067 , H04L2025/0349
摘要： A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.
摘要翻译： 决策反馈均衡器（DFE）和方法包括至少两个路径。 每个路径包括以下内容。 加法器被配置为将输入与从不同路径反馈的第一反馈分接相加。 锁存器耦合到加法器以接收加法信号作为输入。 锁存器包括透明状态，并且锁存器的输出被用作到到不同路径的加法器的反馈路径中的第一抽头，其中在透明状态期间采用反馈路径中的部分分辨的第一抽头以提供一个 软判决在锁存器的硬判决之前提供校正信息。
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20.发明授权Timing recovery method and apparatus for an input/output bus with link redundancy 有权具有链路冗余的输入/输出总线的定时恢复方法和装置公开(公告)号：US08774228B2
公开(公告)日：2014-07-08
申请号：US13157968
申请日：2011-06-10
IPC分类号： H04J3/06
CPC分类号： H04L7/10 , H04L7/0337
摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.
摘要翻译： 提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。 并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数 。 输入数据是n个通道的非校准数据，是m个通道的校准数据。 接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第 多个数据接收器，用于在任何给定时间仅对校准数据进行采样。
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