公开(公告)号：US20070167014A1

公开(公告)日：2007-07-19

申请号：US11543200

申请日：2006-10-05

Applicant: Ilyoung Yoon ,  Jae Ouk Choo ,  JaEung Koo

Inventor： Ilyoung Yoon ,  Jae Ouk Choo ,  JaEung Koo

IPC: H01L21/461

CPC classification number: H01L21/76819 ,  H01L21/31053

Abstract: A chemical mechanical polishing (CMP) method is disclosed for use in the fabrication of a semiconductor device having dense and sparse regions. The method uses an abrasive stop layer formed on the dense and sparse regions to control polishing of a material layer formed on the abrasive stop layer by a rigid, fixed abrasive polishing pad.

Abstract translation: 公开了用于制造具有致密和稀疏区域的半导体器件的化学机械抛光（CMP）方法。 该方法使用形成在致密和稀疏区域上的研磨停止层来控制通过刚性固定的研磨抛光垫在研磨停止层上形成的材料层的抛光。

公开(公告)号：US07785951B2

公开(公告)日：2010-08-31

申请号：US11831223

申请日：2007-07-31

Applicant: Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

Inventor： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

Abstract: Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

公开(公告)号：US20100007021A1

公开(公告)日：2010-01-14

申请号：US12499199

申请日：2009-07-08

Applicant: Jae-Ouk Choo ,  Il-Young Yoon ,  Tae-Hoon Lee ,  Kyoung-Woo Lee

Inventor： Jae-Ouk Choo ,  Il-Young Yoon ,  Tae-Hoon Lee ,  Kyoung-Woo Lee

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76828 ,  H01L23/522 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices including a substrate and an uppermost insulating layer formed on the substrate and having pores is provided. A conductive wiring is provided in the uppermost insulating layer. Dummy vias are provided, each penetrating the uppermost insulating layer, being adjacent to the conductive wiring, and having a space therein. Related methods of fabricating semiconductor devices are also provided.

Abstract translation: 提供了包括衬底和形成在衬底上并具有孔的最上层绝缘层的半导体器件。 导电布线设置在最上层的绝缘层中。 提供虚拟通孔，每个穿过最上层的绝缘层，邻近导电布线并且在其中具有空间。 还提供了制造半导体器件的相关方法。

公开(公告)号：US20090280637A1

公开(公告)日：2009-11-12

申请号：US12453326

申请日：2009-05-07

Applicant: Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

Inventor： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31695

Abstract: Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层 半导体器件。 该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔， 形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

公开(公告)号：US20080153253A1

公开(公告)日：2008-06-26

申请号：US12003301

申请日：2007-12-21

Applicant: Il-young Yoon ,  Jae-ouk Choo ,  Nam-jin Jung ,  Dong-hun Kim ,  Han-woo Lee ,  Gyu-nam Kim

Inventor： Il-young Yoon ,  Jae-ouk Choo ,  Nam-jin Jung ,  Dong-hun Kim ,  Han-woo Lee ,  Gyu-nam Kim

IPC: H01L21/762 ,  B24B1/00

CPC classification number: B24B37/26 ,  B24B37/044 ,  B24B37/245 ,  C09G1/00 ,  C09G1/04 ,  H01L21/31053 ,  H01L21/76224

Abstract: A chemical mechanical polishing process and a method of fabricating a semiconductor device using the same are provided. The chemical mechanical polishing process includes applying a polishing activation solution with a reduced surface energy, wherein the polishing activation solution includes a surfactant; and polishing the object using the polishing activation solution. The method of fabrication includes forming a mask layer pattern on a semiconductor substrate, etching the substrate using the mask layer pattern as an etching mask, forming an insulating layer over a trench, and performing the chemical mechanical polishing above, wherein the object to be polished is the insulating layer.

Abstract translation: 提供化学机械抛光工艺和制造使用其的半导体器件的方法。 化学机械抛光工艺包括施加具有降低的表面能的抛光活化溶液，其中抛光活化溶液包括表面活性剂; 并使用抛光活化溶液抛光物体。 制造方法包括在半导体衬底上形成掩模层图案，使用掩模层图案蚀刻衬底作为蚀刻掩模，在沟槽上形成绝缘层，并进行上述化学机械抛光，其中待抛光的物体 是绝缘层。

公开(公告)号：US20080081476A1

公开(公告)日：2008-04-03

申请号：US11831223

申请日：2007-07-31

Applicant: Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

Inventor： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC: H01L21/302 ,  H01L21/31

CPC classification number: H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

Abstract: Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

公开(公告)号：US20080079087A1

公开(公告)日：2008-04-03

申请号：US11851500

申请日：2007-09-07

Applicant: Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

Inventor： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

Abstract translation: 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US20090286453A1

公开(公告)日：2009-11-19

申请号：US12385704

申请日：2009-04-16

Applicant: Il-young Yoon ,  Tae-hoon Lee ,  Jae-ouk Choo

Inventor： Il-young Yoon ,  Tae-hoon Lee ,  Jae-ouk Choo

IPC: B24B49/04 ,  B24B1/00

CPC classification number: B24B37/042 ,  B24B49/04

Abstract: In accordance with at least one example embodiment, a method of chemical-mechanical polishing includes re-polishing a polished layer on a wafer based on a measured thickness of the polished layer. In accordance with at least one example embodiment, an apparatus for chemical-mechanical polishing may include a thickness measuring unit configured to measure a thickness of a polished surface on a wafer and to determine a re-polishing time based on the measured thickness. In accordance with example embodiments, a thickness deviation between different lots, wafers, or chips inside a wafer is reduced regardless of the durability of a polishing pad, a polishing head, or a disk used in a polishing apparatus.

Abstract translation: 根据至少一个示例性实施例，化学机械抛光的方法包括基于所测量的抛光层的厚度在晶片上重新抛光抛光层。 根据至少一个示例性实施例，用于化学机械抛光的设备可以包括厚度测量单元，其被配置为测量晶片上的抛光表面的厚度并且基于测量的厚度来确定重新抛光时间。 根据示例性实施例，晶片内的不同批次，晶片或芯片之间的厚度偏差减小，而与研磨装置中使用的抛光垫，抛光头或盘的耐久性无关。

公开(公告)号：US07595253B2

公开(公告)日：2009-09-29

申请号：US11797827

申请日：2007-05-08

Applicant: II-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

Inventor： II-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

IPC: H01L21/76

CPC classification number: H01L21/31053 ,  H01L21/76229

Abstract: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

Abstract translation: 示例性实施例提供半导体器件及其形成方法。 根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。 封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。 结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

公开(公告)号：US20080081406A1

公开(公告)日：2008-04-03

申请号：US11750491

申请日：2007-05-18

Applicant: Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

Inventor： Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

IPC: H01L29/739

CPC classification number: H01L21/823425 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

Abstract: A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.

Abstract translation: 一种制造半导体器件的方法，包括在PMOS区上提供包括PMOS区和PMOS栅电极的NMOS区和在NMOS栅区上的NMOS栅电极的衬底，所述衬底在形成的PMOS区上形成应力衬垫 PMOS晶体管上的PMOS栅极和NMOS区域上形成有NMOS栅电极的NMOS区域，并以惰性蒸气气氛，选择性地将辐射施加到形成在PMOS区域和NMOS区域中的任一个上的应力衬垫上。