公开(公告)号：US6111737A

公开(公告)日：2000-08-29

申请号：US267490

申请日：1999-03-11

Applicant: David J. Baldwin ,  Ross E. Teggatz ,  John H. Carpenter, Jr. ,  Joseph A. Devore

Inventor： David J. Baldwin ,  Ross E. Teggatz ,  John H. Carpenter, Jr. ,  Joseph A. Devore

IPC: H01L27/02 ,  H02H3/20

CPC classification number: H01L27/0251

Abstract: An internal circuitry protection scheme which protects on-IC circuitry when an external regulator voltage pin is shorted to a higher voltage. The circuit prevents damage to the on-die circuitry that is on the internal voltage rail, by clamping the received voltage, thereby eliminating the chance of damaging the on die circuitry. The circuit offers protection even if the voltage difference is large, but the difference remains small between the internal rail and the external regulated voltage under normal operation.

Abstract translation: 内部电路保护方案，当外部稳压器电压引脚短路到较高电压时，保护IC内部电路。 该电路通过钳位接收到的电压来防止损坏内部电压轨上的片上电路，从而消除了损坏管芯电路的可能性。 即使电压差大，电路也能提供保护，但在正常工作状态下，内部轨道与外部调节电压之间的差异仍然很小。

公开(公告)号：US5710515A

公开(公告)日：1998-01-20

申请号：US480063

申请日：1995-06-07

Applicant: Ross E. Teggatz ,  Joseph A. Devore ,  Stephen L. Sutton ,  Ganapathy R. Subramaniam

Inventor： Ross E. Teggatz ,  Joseph A. Devore ,  Stephen L. Sutton ,  Ganapathy R. Subramaniam

IPC: G01K7/01 ,  G01R31/28 ,  G01R31/30 ,  G01R31/3167 ,  H01L23/34 ,  G01R31/02 ,  G01R31/00 ,  G08B21/00

CPC classification number: H01L23/34 ,  G01K7/01 ,  G01R31/30 ,  G01R31/3167 ,  H01L2924/0002

Abstract: A testable temperature warning circuit (120) in an integrated circuit substrate (124) provides a warning if the substrate temperature exceeds a critical temperature. A programming circuit (140) controls a selection, circuit (128) to establish a programmably selectable temperature at either the critical temperature or a second predetermined temperature lower than the critical temperature to enable the warning circuit operation to be tested at a temperature lower than the critical temperature. In one embodiment, the selection circuit 128 comprises a current source that produces a voltage drop across the resistor 121 and base-emitter of the transistor 122 produces a substrate temperature indicating current of magnitude related to the temperature of the substrate. The substrate temperature indicating current at the second temperature is extrapolatingly related to the substrate temperature indicating current at the critical temperature. A method is also presented for testing a temperature warning circuit fabricated in an integrated circuit substrate.

Abstract translation: 如果衬底温度超过临界温度，则集成电路衬底（124）中的可测温度警告电路（120）提供警告。 编程电路（140）控制选择电路（128）在临界温度或低于临界温度的第二预定温度下建立可编程选择的温度，以使报警电路操作能够在低于 临界温度。 在一个实施例中，选择电路128包括在电阻器121上产生电压降的电流源，并且晶体管122的基极 - 发射极产生指示与衬底温度相关的电流幅度的衬底温度。 指示在第二温度下的电流的衬底温度与指示临界温度下的电流的衬底温度外推相关。 还提出了一种用于测试在集成电路基板中制造的温度警告电路的方法。

公开(公告)号：US06600205B2

公开(公告)日：2003-07-29

申请号：US10062215

申请日：2002-02-01

Applicant: John H. Carpenter, Jr. ,  Joseph A. Devore ,  Toru Tanaka

Inventor： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Toru Tanaka

IPC: H01L2900

CPC classification number: H01L21/823493 ,  H01L27/088 ,  H01L29/1087

Abstract: A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.

Abstract translation: 公开了一种高耐压晶体管（30; 30'）。 晶体管（30; 30'）形成为阱布置，其中浅的，重掺杂的阱（44）至少部分地设置在更深，更轻掺杂的阱（50）内，两者都形成为外延层 （42）的（43）。 深阱（50）本身也用于形成高压晶体管，而较浅的阱（44）本身用于低电压，高性能的晶体管。 这种结构允许在高偏压应用中使用高性能和精确匹配的晶体管，而不用担心体对衬底（或“背栅极到衬底”）结击穿。

公开(公告)号：US06486740B1

公开(公告)日：2002-11-26

申请号：US09651568

申请日：2000-08-28

Applicant: David J. Baldwin ,  Ross E. Teggatz ,  Joseph A. Devore

Inventor： David J. Baldwin ,  Ross E. Teggatz ,  Joseph A. Devore

IPC: H03F114

CPC classification number: H03F1/14

Abstract: One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.

Abstract translation: 本发明的一个方面是一种集成电路（10或110），包括在其频率响应中具有至少两个极的放大器（11或111）和输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2， M3，M4，AC1）耦合到放大器（11或111）的输出节点（30）。 输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2，M3，M4，AC1）可操作以产生与耦合到输出节点（30）的输出负载（50）的阻抗成比例的反馈信号， ，并且响应于至少两个极之间的反馈信号，在放大器（11或111）的频率响应中产生零。

公开(公告)号：US06469884B1

公开(公告)日：2002-10-22

申请号：US09472710

申请日：1999-12-24

Applicant: John H. Carpenter, Jr. ,  Joseph A. Devore ,  Reed Adams ,  Ross Teggatz

Inventor： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Reed Adams ,  Ross Teggatz

IPC: H02H322

CPC classification number: G11C17/18

Abstract: An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN3, MN1) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (Vmain). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MNmain) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.

Abstract translation: 具有至少一个可编程熔丝（F1）和ESD电路（MN3，MN1）的集成电路（10）防止当在主电压电位（Vmain）上存在电压瞬变时熔丝（F1）被无意地烧断。 ESD电路优选地包括MOSFET开关，其由于电压瞬变而被耦合以比主熔丝编程开关（MNmain）更快地接通，从而确保主开关在电压瞬变期间保持关断以防止熔丝的无意的吹动 F1。 该电路非常适用于可编程逻辑器件（PLD），允许低至6伏的读取电压，并允许高达40伏的编程电压。

公开(公告)号：US06376870B1

公开(公告)日：2002-04-23

申请号：US09658202

申请日：2000-09-08

Applicant: John H. Carpenter, Jr. ,  Joseph A. Devore ,  Toru Tanaka ,  Ross E. Teggatz

Inventor： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Toru Tanaka ,  Ross E. Teggatz

IPC: H01L2972

CPC classification number: H01L21/823493 ,  H01L27/088 ,  H01L29/1087

Abstract: A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.

Abstract translation: 公开了一种高耐压晶体管（30; 30'）。 晶体管（30; 30'）形成为阱布置，其中浅的，重掺杂的阱（44）至少部分地设置在更深，更轻掺杂的阱（50）内，两者都形成为外延层 （42）的（43）。 深阱（50）本身也用于形成高压晶体管，而较浅的阱（44）本身用于低电压，高性能的晶体管。 这种结构允许在高偏压应用中使用高性能和精确匹配的晶体管，而不用担心体对衬底（或“背栅极到衬底”）结击穿。

公开(公告)号：US06268755B1

公开(公告)日：2001-07-31

申请号：US08963836

申请日：1997-11-04

Applicant: R. Travis Summerlin ,  Joseph A. Devore ,  William E. Grose

Inventor： R. Travis Summerlin ,  Joseph A. Devore ,  William E. Grose

IPC: H03K190185

CPC classification number: H03K19/018585 ,  H03K19/00361

Abstract: A voltage level shifting circuit (60) and method for accomplishing a voltage level change includes a voltage level shifting circuit (65) to change an input voltage to a shifted voltage level. A second stage (67) is connected between a voltage source at the shifted voltage level (68) and the reference potential. The second stage (67) includes active devices (66,82) that are controlled by the voltage level shifting circuit (65). The second stage (67) also includes slope resistors (86,88) connected in series between the active devices (66,82) of the second stage (67).

Abstract translation: 电压电平移动电路（60）和用于实现电压电平变化的方法包括将输入电压改变到移位的电压电平的电压电平移位电路（65）。 第二级（67）连接在变换的电压电平（68）的电压源和参考电位之间。 第二级（67）包括由电压电平移位电路（65）控制的有源器件（66,82）。 第二级（67）还包括串联连接在第二级（67）的有源器件（66,82）之间的斜率电阻器（86,88）。

公开(公告)号：US06236098B1

公开(公告)日：2001-05-22

申请号：US09061452

申请日：1998-04-16

Applicant: Taylor R. Efland ,  R. Travis Summerlin ,  Joseph A. Devore

Inventor： Taylor R. Efland ,  R. Travis Summerlin ,  Joseph A. Devore

IPC: H01L31058

CPC classification number: H01L23/34 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2924/3011

Abstract: An integrated circuit chip (10, 50, 100) may comprise an integrated circuit (14, 54, 108, 110, 112) formed in a semiconductor layer (12, 52, 102). A thermal contact (16, 56, 116) may be formed at a high temperature region of the integrated circuit (14, 54, 108, 110, 112). A thick plated metal layer (40, 80, 140) may be generally isolated from the integrated circuit (14, 54, 108, 110, 112). The thick plated metal layer (40, 80, 140) may include a base (42, 82, 142) and an exposed surface (44, 84, 144) opposite the base (42, 82, 142). The base (42, 82, 142) may be coupled to the thermal contact (16, 56, 116) to receive thermal energy of the high temperature region. The exposed surface (44, 84, 144) may dissipate thermal energy received by the thick plated metal layer (40, 80, 140).

Abstract translation: 集成电路芯片（10,50,100）可以包括形成在半导体层（12,52,102）中的集成电路（14,54,108,110,112）。 可以在集成电路（14,54,108,110,112）的高温区域形成热接触（16,56,116）。 厚电镀金属层（40,80,140）可以通常与集成电路（14,54,108,110,112）隔离。 厚电镀金属层（40,80,140）可以包括基部（42,82,142）和与基部（42,82,142）相对的暴露表面（44,84,144）。 基座（42,82,142）可以联接到热接触件（16,56,116）以接收高温区域的热能。 暴露表面（44,84,144）可以消散由厚镀金属层（40,80,140）接收的热能。

公开(公告)号：US06169309A

公开(公告)日：2001-01-02

申请号：US09159947

申请日：1998-09-24

Applicant: Ross E. Teggatz ,  Joseph A. Devore ,  David J. Baldwin

Inventor： Ross E. Teggatz ,  Joseph A. Devore ,  David J. Baldwin

IPC: H01L2976

CPC classification number: H01L27/0251

Abstract: A circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a first terminal coupled to a power supply and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well 504 and a shunting bipolar transistor is formed between the n-well 504 and an n-doped guard ring 500 formed adjacent to the n-well in the p-doped substrate 508.

Abstract translation: 用于保护晶体管免受电瞬态的电路。 电路包括耦合在耦合到电源的第一端子和受保护晶体管的控制端子之间的第一二极管。 该电路还包括将受保护晶体管的控制端耦合到参考电位的第二二极管和电阻器。 第二晶体管耦合到分流到保护晶体管。 第二晶体管的控制端子上的电压由通过电阻器的电流决定。 实施例可以在集成电路中实现，其中第二分流晶体管由形成有保护晶体管的半导体主体内的寄生元件形成。 在一个实施例中，被保护的MOS晶体管形成在n阱504中，并且分流双极晶体管形成在n阱504和邻近p掺杂衬底中的n阱附近形成的n掺杂保护环500之间 508。

公开(公告)号：US6144070A

公开(公告)日：2000-11-07

申请号：US141496

申请日：1998-08-28

Applicant: Joseph A. Devore ,  Ross E. Teggatz ,  David J. Baldwin

Inventor： Joseph A. Devore ,  Ross E. Teggatz ,  David J. Baldwin

IPC: H01L23/60 ,  H01L27/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L23/58 ,  H01L23/62 ,  H01L29/94

CPC classification number: H01L29/7816 ,  H01L23/60 ,  H01L27/0262 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/7393 ,  H01L29/7436 ,  H01L29/7813 ,  H01L2924/0002

Abstract: A transistor including a source region 506 in a semiconductor body 502; a bulk region 508 in the semiconductor body adjacent the source region; a drain region in the semiconductor body adjacent the bulk region but opposite the source region, the drain region including doped regions 504,514 of n and p dopant types; and a field plate 516 formed over the semiconductor body adjacent the drain region between the drain region and the bulk region.

Abstract translation: 一种晶体管，包括半导体本体502中的源极区域506; 邻近源极区域的半导体本体区域508; 所述半导体本体中的漏极区域邻近所述体区域但与所述源极区域相对，所述漏极区域包括n和p掺杂剂类型的掺杂区域504,514; 以及形成在半导体本体上的与漏极区域和主体区域之间的漏极区域相邻的场板516。