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11.发明授权Method for preparing PLZT, PZT and PLT sol-gels and fabricating ferroelectric thin films 失效制备PLZT，PZT和PLT溶胶凝胶并制备铁电薄膜的方法
公开(公告)号：US4946710A
公开(公告)日：1990-08-07
申请号：US057323
申请日：1987-06-02
IPC分类号： C04B35/491 , H01L21/316 , H01L41/24
CPC分类号： H01L21/31691 , C04B35/491 , C23C18/1216 , C23C18/1245 , C23C18/1254
摘要： A method to produce thin films suitable for fabricating ferroelectric thin films. The method provides for selection of the predetermined amounts of lead, lanthanum, zirconium, and titanium precursors which are soluble in different solvents. Dissolving predetermined amounts of the precursors in their respective solvents in proportions such that hydrolyze reaction rate for each metal precursor will be approximately equal. The precursors and solvents are mixed, and water is added to begin a hydrolysis reaction. After the hydrolysis the solution is heated to drive off the excess water and solvent to promote the formation of a sol-gel. The sol-gel is then applied to a thin substrate and sintered to produce the ferroelectric film.
摘要翻译： 一种制造适合于制造铁电薄膜的薄膜的方法。 该方法提供了可溶于不同溶剂的预定量的铅，镧，锆和钛前体的选择。 在各自溶剂中溶解预定量的前体，使得每种金属前体的水解反应速率将近似相等。 将前体和溶剂混合，加入水开始水解反应。 水解后，将溶液加热以除去过量的水和溶剂以促进溶胶 - 凝胶的形成。 然后将溶胶 - 凝胶施加到薄的衬底上并烧结以产生铁电体膜。
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公开(公告)号：US08787063B2
公开(公告)日：2014-07-22
申请号：US13559531
申请日：2012-07-26
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C27/005
摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a value determined by a data value having at least three states to be stored in the ferroelectric memory cell currently connected to the write line. A read circuit measures the charge stored in the ferroelectric memory cell currently connected to the read line.
摘要翻译： 公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。 铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。 每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。 写入电路使由具有至少三个状态的数据值确定的值存储在当前连接到写入线的铁电存储单元中。 读取电路测量存储在当前连接到读取线的铁电存储器单元中的电荷。
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公开(公告)号：US20120134196A1
公开(公告)日：2012-05-31
申请号：US12956845
申请日：2010-11-30
CPC分类号： G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C27/005
摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.
摘要翻译： 公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。 铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。 每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。 写入电路使电荷存储在当前连接到写入线的强电介质存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。 读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。
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公开(公告)号：US08018754B1
公开(公告)日：2011-09-13
申请号：US07582672
申请日：1990-09-14
CPC分类号： G11C11/22 , G11C11/5657
摘要： A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.
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公开(公告)号：US5926412A
公开(公告)日：1999-07-20
申请号：US864152
申请日：1992-04-02
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Architectures for a ferroelectric memory which avoids the half select phenomenon and the problems associated with destructive readout. Non-destructive readout is provided by measuring current through the ferroelectric memory as a measure of its resistance. Information is stored in the ferroelectric memory element by altering its resistance through a polarizing voltage. The half select phenomenon is avoided by using isolation techniques. In various embodiments, zener diodes or bipolar junction transistors are used for isolation.
摘要翻译： 用于铁电存储器的架构，避免了半选择现象和与破坏性读出相关的问题。 通过测量通过铁电存储器的电流作为其电阻的量度来提供非破坏性读出。 信息通过极化电压改变其电阻而被存储在铁电存储元件中。 通过使用隔离技术避免了半选择现象。 在各种实施例中，齐纳二极管或双极结型晶体管用于隔离。
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公开(公告)号：US5804850A
公开(公告)日：1998-09-08
申请号：US633853
申请日：1996-04-16
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/92 , H01L31/119
CPC分类号： H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.
摘要翻译： 一种铁电体电容器结构及其制造方法。 电容器包括具有与第一欧姆材料层接触的Pt层的底部电极。 电容器电介质由掺杂有大于+4的氧化态的元素的钛酸铅锆层构成。 电容器的顶部电极由与Pt层接触的第二层欧姆材料构成。 优选的欧姆材料是LSCO; 尽管也可以使用RuO 2。 电容器优选地构造在FET的漏极上，使得电容器的底部电极连接到FET的漏极。 所得到的电容器结构具有低压印和低疲劳。
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17.发明授权Method for constructing ferroelectric capacitor-like structures on silicon dioxide surfaces 失效在二氧化硅表面上构造铁电电容器状结构的方法
公开(公告)号：US5593914A
公开(公告)日：1997-01-14
申请号：US616526
申请日：1996-03-19
IPC分类号： H01L21/02 , H01L27/115 , H01L21/70
CPC分类号： H01L27/11502 , H01L28/55 , Y10S148/014
摘要： A method for fabricating an integrated circuit having at least one integrated circuit component fabricated in a silicon substrate and a second device that is to be fabricated on a silicon oxide layer that covers the integrated circuit component. The integrated circuit component has a terminal that is to be connected a corresponding terminal on the second device. The second device includes an electrode structure in contact with a dielectric component that includes a layer of ferroelectric material. In the method of the present invention, a boundary layer comprising non-conducting polysilicon is deposited over the silicon oxide layer. The electrode structure is then fabricated by depositing one or more layers over the boundary layer. The ferroelectric layer is then deposited over the electrode structure and etched to provide the dielectric component. The boundary layer is then removed utilizing an etchant that etches silicon oxide much slower than polysilicon.
摘要翻译： 一种用于制造集成电路的方法，所述集成电路具有制造在硅衬底中的至少一个集成电路部件和将被制造在覆盖所述集成电路部件的氧化硅层上的第二器件。 集成电路部件具有要连接到第二装置上的相应端子的端子。 第二装置包括与包括铁电材料层的电介质部件接触的电极结构。 在本发明的方法中，在氧化硅层上沉积包含非导电多晶硅的边界层。 然后通过在边界层上沉积一个或多个层来制造电极结构。 然后将铁电层沉积在电极结构上并被蚀刻以提供电介质成分。 然后利用蚀刻氧化硅比多晶硅慢的蚀刻剂去除边界层。
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18.发明授权
公开(公告)号：US5212620A
公开(公告)日：1993-05-18
申请号：US845064
申请日：1992-03-03
IPC分类号： H01L27/04 , G11C11/22 , H01G4/10 , H01G7/00 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： H01L28/55 , Y10T29/435
摘要： An improved method for constructing integrated circuit structures in which a buffer SiO.sub.2 layer is used to separate various components comprising ferroelectric materials or platinum is disclosed. The invention prevents interactions between the SiO.sub.2 buffer layer and the ferroelectric materials. The invention also prevents the cracking in the SiO.sub.2 which is commonly observed when the SiO.sub.2 layer is deposited directly over a platinum region on the surface of the circuit. The present invention utilizes a buffer layer of material which is substantially inert with respect to the ferroelectric material and which is also an electrical insulator to separate the SiO.sub.2 layer from the ferroelectric material and/or the platinum regions.
摘要翻译： 公开了一种用于构建集成电路结构的改进方法，其中使用缓冲层SiO 2层分离包含铁电材料或铂的各种组分。 本发明防止了SiO 2缓冲层与铁电材料之间的相互作用。 本发明还防止当SiO 2层直接沉积在电路表面上的铂区域上时通常观察到的SiO 2中的开裂。 本发明利用了相对于铁电材料基本上是惰性的材料的缓冲层，其也是用于将SiO 2层与铁电材料和/或铂区分离的电绝缘体。
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公开(公告)号：US5070385A
公开(公告)日：1991-12-03
申请号：US424809
申请日：1989-10-20
IPC分类号： H01L21/8247 , G11C11/22 , H01L21/8246 , H01L27/105 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22
摘要： An improved non-volatile variable resistance element is disclosed. The resistive element is based on a semiconductor having a resistivity which is determined by the state of polarization of a ferroelectric layer.
摘要翻译： 公开了一种改进的非易失性可变电阻元件。 电阻元件基于具有由铁电层的极化状态确定的电阻率的半导体。
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20.发明授权Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption 有权嵌入式非易失性存储器电路，用于在电源中断期间实现逻辑功能公开(公告)号：US08824186B2
公开(公告)日：2014-09-02
申请号：US13543652
申请日：2012-07-06
申请人： Joseph T. Evans, Jr.
发明人： Joseph T. Evans, Jr.
IPC分类号： G11C11/22
CPC分类号： H03K19/0008 , G11C7/1006 , G11C11/22 , G11C11/221 , G11C11/2297 , H03K19/096
摘要： A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.
摘要翻译： 公开了具有自主铁电存储器锁存器（AML）的电路。 AML以AML输入，AML输出，第一AML电源触点，第二AML电源触点和AML状态为特征，以及与AML输入或AML输出之一串联的第一开关。 开关被定位成在第一和第二AML电源触点之间提供电力时防止AML的状态改变。 在本发明的一个方面，电路可以包括与AML输入或AML输出中的另一个串联的第二开关和与AML输入或AML输出串联的锁存器。 锁存器的定位使得AML输出和AML输入之间不存在直接回路。
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