公开(公告)号：US20050188915A1

公开(公告)日：2005-09-01

申请号：US10916254

申请日：2004-08-11

Applicant: Konstantin Bourdelle ,  Ian Cayrefourcq ,  Kennard Mark

Inventor： Konstantin Bourdelle ,  Ian Cayrefourcq ,  Kennard Mark

IPC: H01L21/20 ,  C30B1/00 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/0262 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract translation: 本发明涉及一种制造晶片的方法，该方法包括第一材料的单晶体体衬底和具有与第一材料的晶格不同的晶格的第二材料的至少一个外延层。 本发明提供了一种制造晶片的方法，其中可以以低成本以高效率和高质量在衬底上生长与衬底晶格失配的层。 包括粗糙化步骤以粗化本体衬底的表面，并且包括生长步骤，用于在粗糙表面上生长第二材料，数量较少的穿透位错和与外延生长的第二材料相比增强的应变松弛 抛光表面。

公开(公告)号：US09275892B2

公开(公告)日：2016-03-01

申请号：US13990539

申请日：2011-11-23

Applicant: Nicolas Daix ,  Konstantin Bourdelle

Inventor： Nicolas Daix ,  Konstantin Bourdelle

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/762

CPC classification number: H01L21/76254

Abstract: A method of transferring a layer from a donor substrate onto a receiving substrate comprises ionic implantation of at least one species into the donor substrate and forming a layer of concentration of the species intended to form microcavities or platelets; bonding the donor substrate with the receiving substrate by wafer bonding; and splitting at high temperature to split the layer in contact with the receiving substrate by cleavage, at a predetermined cleavage temperature, at the layer of microcavities or platelets formed in the donor substrate. The method further comprises, after the first implantation step and before the splitting step, ionic implantation of silicon ions into the donor substrate to form a layer of concentration of silicon ions in the donor substrate, the layer of concentration of silicon ions at least partially overlapping the layer of concentration of the species intended to form microcavities or platelets.

Abstract translation: 将一层从供体衬底转移到接收衬底上的方法包括将至少一种物质离子注入供体底物并形成旨在形成微腔或血小板的物质浓度层; 通过晶片接合将施主衬底与接收衬底结合; 并在高温下分裂，以在预定的切割温度下，在形成于供体底物中的微腔或血小板层处切割以分离接触基底的层。 该方法还包括在第一注入步骤之后并且在分离步骤之前，将硅离子离子注入供体衬底以在供体衬底中形成硅离子浓度层，所述硅离子的浓度层至少部分重叠 旨在形成微腔或血小板的物种的浓度层。

公开(公告)号：US09035474B2

公开(公告)日：2015-05-19

申请号：US12793515

申请日：2010-06-03

Applicant: Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

IPC: H01L23/544 ,  H01L21/762 ,  H01L21/18 ,  H01L21/20

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76251

Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.

Abstract translation: 本发明涉及一种制造半导体衬底的方法，特别是通过提供一个施主衬底和一个把手衬底来制造绝缘体上半导体衬底，通常形成一个或多个掺杂区域的图案，通常在处理衬底内部，然后附着 例如通过分子结合施主衬底和处理衬底以获得施主手柄化合物。

公开(公告)号：US07799651B2

公开(公告)日：2010-09-21

申请号：US12165365

申请日：2008-06-30

Applicant: Carlos Mazure ,  Ian Cayrefourcq ,  Konstantin Bourdelle

Inventor： Carlos Mazure ,  Ian Cayrefourcq ,  Konstantin Bourdelle

IPC: H01L21/331

CPC classification number: H01L21/187 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/76254 ,  H01L29/045

Abstract: The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate.

Abstract translation: 本发明涉及一种处理由半导体材料制成的结构的方法，其中该结构包括限定具有缺陷的公共接口的第一和第二基板。 所述方法包括形成称为所述无组织层的层，所述层包括所述界面，其中所述晶格的至少一部分被混杂; 并重新组织无组织层的晶格，以迫使缺陷更深地进入第一衬底。

公开(公告)号：US07449394B2

公开(公告)日：2008-11-11

申请号：US11179713

申请日：2005-07-11

Applicant: Takeshi Akatsu ,  Nicolas Daval ,  Nguyet-Phuong Nguyen ,  Olivier Rayssac ,  Konstantin Bourdelle

Inventor： Takeshi Akatsu ,  Nicolas Daval ,  Nguyet-Phuong Nguyen ,  Olivier Rayssac ,  Konstantin Bourdelle

IPC: H01L21/46

CPC classification number: H01L21/76254

Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface; coimplanting two different atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer; bonding the free surface of the second layer to a host wafer; and supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer. Advantageously, the donor wafer includes a SiGe layer, and the co-implantation of atomic species is conducted according to implantation parameters adapted to enable a first species to form the zone of weakness in the SiGe layer, and to enable a second species to provide a concentration peak located beneath the zone of weakness in the donor wafer to thus minimize surface roughness resulting from detachment at the zone of weakness.

Abstract translation: 描述形成半导体结构的方法。 在一个实施例中，该技术包括提供在第一层上具有第一半导体层和第二半导体层并具有自由表面的施主晶片; 通过第二层的自由表面共同植入两种不同的原子物质，以形成第一层中的弱区; 将第二层的自由表面粘合到主晶片; 并且在弱化区域提供能量以分散包含主晶片，第二层和第一层的一部分的半导体结构。 有利地，施主晶片包括SiGe层，并且根据适于使第一种类形成SiGe层中的弱点区域的植入参数来进行原子物质的共同注入，并且使得第二物质能够提供 浓度峰位于供体晶片中的弱点之下，从而使得在弱化区分离导致的表面粗糙度最小化。

公开(公告)号：US07387947B2

公开(公告)日：2008-06-17

申请号：US11305444

申请日：2005-12-16

Applicant: Ian Cayrefourcq ,  Carlos Mazure ,  Konstantin Bourdelle

Inventor： Ian Cayrefourcq ,  Carlos Mazure ,  Konstantin Bourdelle

IPC: H01L21/20

CPC classification number: H01L21/76254

Abstract: The present invention relates to a method for transferring a thin useful layer from a donor substrate having an ordered crystalline structure to a receiver substrate. The method includes creation of a weakened zone in the donor substrate to define the layer to be transferred from the donor substrate. The crystalline structure of a surface region of the donor substrate is disturbed so as to create a disturbed superficial region within the thickness of the donor substrate, and thus define a disturbance interface between the disturbed superficial region and a subjacent region of the donor substrate for which the crystalline structure remains unchanged. Next, the donor substrate is subjected to a recrystallization annealing in order to at least partial recrystallize of the disturbed region, starting from the crystalline structure of the subjacent region of the donor substrate, and to create a zone of crystalline defects in the plane of the disturbance interface. One or several species are introduced into the thickness of the donor substrate to create the weakened zone, with the species being introduced with introduction parameters that are adjusted to introduce a maximum number of species at the zone of crystalline defects.

Abstract translation: 本发明涉及一种从具有有序晶体结构的施主衬底向接收衬底转移薄有用层的方法。 该方法包括在施主衬底中产生弱化区以限定要从供体衬底转移的层。 施主衬底的表面区域的晶体结构受到干扰，从而在施主衬底的厚度内产生干扰的表面区域，从而限定受干扰的表面区域和施主衬底的下部区域之间的扰动界面， 晶体结构保持不变。 接下来，对施主衬底进行再结晶退火，以便从施主衬底的下部区域的结晶结构开始至少部分地重新结晶受阻区域，并在该平面内产生晶体缺陷区域 扰动界面。 将一个或多个物质引入施主衬底的厚度以产生弱化区域，其中引入物质，引入参数被调整以在晶体缺陷区域引入最大数量的物质。

公开(公告)号：US09018678B2

公开(公告)日：2015-04-28

申请号：US13399273

申请日：2012-02-17

Applicant: Nicolas Daval ,  Bich-Yen Nguyen ,  Cecile Aulnette ,  Konstantin Bourdelle

Inventor： Nicolas Daval ,  Bich-Yen Nguyen ,  Cecile Aulnette ,  Konstantin Bourdelle

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/78681 ,  H01L21/76254 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.

Abstract translation: 本发明涉及通过在施主衬底上生长放松的锗层来形成包含III / V材料的半导体层的半导体绝缘体结构的方法; 在锗层上生长至少一层III / V材料; 在松弛的锗层中形成裂开面; 将所述施主衬底的切割部分转移到支撑衬底，其中所述切割部分是在包括所述至少一层III / V材料的所述切割平面处切割的施主衬底的一部分。 本发明还涉及III / V绝缘体上的锗结构，N场效应晶体管（NFET），NFET的制造方法，P场效应晶体管（PFET）及其制造方法 PFET。

公开(公告)号：US20120228672A1

公开(公告)日：2012-09-13

申请号：US13399273

申请日：2012-02-17

Applicant: Nicolas Daval ,  Bich-Yen Nguyen ,  Cecile Aulnette ,  Konstantin Bourdelle

Inventor： Nicolas Daval ,  Bich-Yen Nguyen ,  Cecile Aulnette ,  Konstantin Bourdelle

IPC: H01L29/78 ,  H01L29/267 ,  H01L21/336 ,  H01L21/3105

CPC classification number: H01L29/78681 ,  H01L21/76254 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.

Abstract translation: 本发明涉及通过在施主衬底上生长放松的锗层来形成包含III / V材料的半导体层的半导体绝缘体结构的方法; 在锗层上生长至少一层III / V材料; 在松弛的锗层中形成裂开面; 将所述施主衬底的切割部分转移到支撑衬底，其中所述切割部分是在包括所述至少一层III / V材料的所述切割平面处切割的施主衬底的一部分。 本发明还涉及III / V绝缘体上的锗结构，N场效应晶体管（NFET），NFET的制造方法，P场效应晶体管（PFET）及其制造方法 PFET。

公开(公告)号：US08241942B2

公开(公告)日：2012-08-14

申请号：US13123661

申请日：2009-09-22

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L21/00 ,  H01L21/30 ,  H01L21/04 ,  H01L21/425

CPC classification number: H01L27/14689 ,  H01L27/1464

Abstract: A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.

Abstract translation: 一种制造背照式图像传感器的方法，包括以下步骤：提供半导体层的第一衬底，特别是硅层，在半导体层上形成电子器件结构，然后仅仅掺杂半导体层。 通过这样做，可以实现改进的光电二极管的掺杂剂分布和电性能，使得最终产品，即图像传感器具有更好的质量。

公开(公告)号：US20110294277A1

公开(公告)日：2011-12-01

申请号：US13093615

申请日：2011-04-25

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76283 ,  H01L21/76275 ,  H01L29/66181

Abstract: The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like.

Abstract translation: 本发明提供了在多层晶片中制造沟槽结构的方法，该多层晶片包括衬底，衬底上的氧化物层和氧化物层上的半导体层。 这些方法包括以下步骤：通过半导体层和氧化物层形成沟槽并延伸到衬底中，并且对所形成的沟槽进行退火处理，使得在沟槽的内表面处，半导体层的一些材料在 至少暴露在沟槽内表面的部分氧化物层的一部分。 根据本发明制造的衬底有利于制造各种半导体器件，例如MOSFET，沟槽电容器等。