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    Image processor and data processing system using the same processor
    11.
    发明授权
    Image processor and data processing system using the same processor 失效
    图像处理器和数据处理系统使用相同的处理器

    公开(公告)号：US6091863A

    公开(公告)日：2000-07-18

    申请号：US523509

    申请日：1995-09-01

    申请人： Keisuke Nakashima ,  Jun Satoh ,  Kazushige Yamagishi ,  Takashi Miyamoto ,  Kenichiro Omura ,  Koyo Katsura ,  Mitsuru Watabe

    发明人： Keisuke Nakashima ,  Jun Satoh ,  Kazushige Yamagishi ,  Takashi Miyamoto ,  Kenichiro Omura ,  Koyo Katsura ,  Mitsuru Watabe

    IPC分类号： G09G5/00 ,  G06F12/00 ,  G06T1/20 ,  G06T11/00 ,  G06T15/04 ,  G06K9/36 ,  G06F15/00 ,  G06K9/54

    CPC分类号： G06T1/20

    摘要： An image processor which is connected to a system bus that connects a processor for forming graphic command related to image processing to a main memory that holds command and original image data, and draws image on the frame buffer based upon said graphic command from said processor, wherein said graphic processor has a data bus change-over unit which connects said system bus to a first data bus that is connected to a graphic data memory holding said graphic command and said original image data, or connects said first data bus to a frame buffer which holds the data to be displayed. The image processor realizes a high-speed processing at a reduced cost by using a graphic memory bus coupled to a graphic processor.

    摘要翻译： 一种图像处理器，其连接到系统总线，该系统总线将用于形成与图像处理有关的图形命令的处理器连接到保存命令和原始图像数据的主存储器，并且基于来自所述处理器的所述图形命令在所述帧缓冲器上绘制图像， 其中所述图形处理器具有数据总线转换单元，其将所述系统总线连接到连接到保存所述图形命令和所述原始图像数据的图形数据存储器的第一数据总线，或将所述第一数据总线连接到帧缓冲器 它保存要显示的数据。 图像处理器通过使用耦合到图形处理器的图形存储器总线以低成本实现高速处理。

    Graphic processing having apparatus for outputting FIFO vacant information
    12.
    发明授权
    Graphic processing having apparatus for outputting FIFO vacant information 失效
    具有用于输出FIFO空闲信息的装置的图形处理

    公开(公告)号：US5717440A

    公开(公告)日：1998-02-10

    申请号：US355151

    申请日：1994-12-06

    申请人： Koyo Katsura ,  Shigeru Matsuo ,  Jun Sato ,  Takashi Sone ,  Yoshikazu Yokota ,  Masahiko Kikuchi

    发明人： Koyo Katsura ,  Shigeru Matsuo ,  Jun Sato ,  Takashi Sone ,  Yoshikazu Yokota ,  Masahiko Kikuchi

    IPC分类号： G06T1/20 ,  G06T11/20 ,  G09G5/02 ,  G09G5/393 ,  G09G5/399 ,  G09G5/00

    CPC分类号： G06T11/203 ,  G06T1/20 ,  G09G5/024 ,  G09G5/393 ,  G09G5/399

    摘要： A graphic processing system including a main memory for storing a program and information correspond to pixels, a main processor for effecting an execution processing of a program transferred from the main memory or from an external device so as to control the system, display/output devices such as a CRT device and a printer for outputting graphic information attained by controlling pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels outputted to the display/output devices, and a graphic processor for receiving a command and parameter information transferred from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or the frame buffer, respectively. The system includes a bus connection switch circuit to be controlled by the graphic processor to effect a connection control between the first and second address buses and between the first and second data buses so as to enable execution of a drawing processing in the main memory connected to a bus on the main processor side and a data transfer between the main memory and the frame buffer.

    摘要翻译： 包括用于存储程序的主存储器和对应于像素的信息的图形处理系统，用于执行从主存储器或从外部设备传送的程序的执行处理以便控制系统的主处理器，显示/输出设备 例如用于输出通过控制以多个维度排列的像素获得的图形信息的CRT设备和打印机，用于存储对应于输出到显示/输出设备的像素的信息的帧缓冲器，以及用于接收命令和参数的图形处理器 从主存储器和/或主处理器传送的信息，用于根据预定的处理过程产生字符和图形数据，并且用于执行包括执行绘图处理的传送控制，以通过第一和第二地址总线传送生成的数据;以及 呼叫到主存储器和/或帧缓冲器的第一和第二数据总线 真诚地 该系统包括由图形处理器控制的总线连接开关电路，以实现第一和第二地址总线之间以及第一和第二数据总线之间的连接控制，以便能够执行与主存储器连接的图形处理 主处理器侧的总线和主存储器与帧缓冲器之间的数据传输。

    Display control device
    15.
    发明授权
    Display control device 失效
    显示控制装置

    公开(公告)号：US5606338A

    公开(公告)日：1997-02-25

    申请号：US309411

    申请日：1994-09-20

    申请人： Hiroshi Takeda ,  Shigeaki Yoshida ,  Koyo Katsura

    发明人： Hiroshi Takeda ,  Shigeaki Yoshida ,  Koyo Katsura

    IPC分类号： G09G5/18 ,  G09G5/12 ,  G09G1/08

    CPC分类号： G09G5/12

    摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.

    摘要翻译： 用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作， 。 当CRTC用作CRT显示系统的主电路时，与垂直扫描计数器的计数信号和CRTC的隔行控制器的输出同步地从同步电路导出同步信号，并将其提供给 其他CRTC的同步终端。 用于控制其他CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。 当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。

    Graphic processor suitable for graphic data tranfers and conversion processes
    18.
    发明授权
    Graphic processor suitable for graphic data tranfers and conversion processes 失效
    图形处理器适用于图形数据传输和转换过程

    公开(公告)号：US5319750A

    公开(公告)日：1994-06-07

    申请号：US942001

    申请日：1992-09-08

    申请人： Shigeru Matsuo ,  Koyo Katsura ,  Jun Sato ,  Takashi Sone ,  Nasakatu Yokoyama

    发明人： Shigeru Matsuo ,  Koyo Katsura ,  Jun Sato ,  Takashi Sone ,  Nasakatu Yokoyama

    IPC分类号： G06T17/00 ,  G06F15/62

    CPC分类号： G06T17/00

    摘要： A graphic processor which controls reading, writing and transfer of graphic data for a display memory that stores graphic data. The processor includes a first unit which stores first address information for addressing the display memory and first pixel address information which points a pixel position in a word specified by the first address information, a second unit which stores second address information for addressing the display memory and second pixel address information which points a pixel position in a word specified by the second address information, a third unit which shifts graphic data of multiple pixels included in two consecutive words to extract continuous 1-word graphic data, and a fourth unit which implements drawing computations pixel-wise concurrently for one word depending on the number of pixels included in a word. Even if transfer source graphic data lies across two consecutive words, the processor fetches the source data in single reading, processes the data word-wise at once, and stores the result in the display memory.

    摘要翻译： 用于控制用于存储图形数据的显示存储器的图形数据的读取，写入和传送的图形处理器。 处理器包括第一单元，其存储用于寻址显示存储器的第一地址信息和指向由第一地址信息指定的字中的像素位置的第一像素地址信息;第二单元，存储用于寻址显示存储器的第二地址信息;以及 指定由第二地址信息指定的字中的像素位置的第二像素地址信息;移动包括在两个连续字中的多个像素的图形数据以提取连续的1字图形数据的第三单元;以及实现绘图的第四单元 根据包含在一个单词中的像素数量，对一个单词进行像素同步的计算。 即使传输源图形数据位于两个连续的字中，处理器以单次读取的方式读取源数据，一次处理数据，并将结果存储在显示存储器中。

    Graphic processing system having bus connection control capable of high-speed parallel drawing processing in a frame buffer and a system memory
    19.
    发明授权
    Graphic processing system having bus connection control capable of high-speed parallel drawing processing in a frame buffer and a system memory 失效
    具有能够在帧缓冲器和系统存储器中进行高速并行绘制处理的总线连接控制的图形处理系统

    公开(公告)号：US5046023A

    公开(公告)日：1991-09-03

    申请号：US105292

    申请日：1987-10-06

    申请人： Koyo Katsura ,  Shigeru Matsuo ,  Jun Sato ,  Takashi Sone ,  Yoshikazu Yokota ,  Masahiko Kikuchi

    发明人： Koyo Katsura ,  Shigeru Matsuo ,  Jun Sato ,  Takashi Sone ,  Yoshikazu Yokota ,  Masahiko Kikuchi

    IPC分类号： G06T1/20 ,  G06T11/20 ,  G09G5/02 ,  G09G5/393 ,  G09G5/399

    CPC分类号： G09G5/393 ,  G06T1/20 ,  G06T11/203 ,  G09G5/024 ,  G09G5/399

    摘要： A graphic processing system including a main memory for storing a program and information corresponding to pixels, a main processor for effecting an execution processing of a program transferred from the main memory or from an external device so as to control the system, display/output devices such as a CRT device and a printer for outputting graphic information attained by controlling pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels outputted to the display/output devices, and a graphic processor for receiving a command and parameter information transferred from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or the frame buffer, respectively. The system also includes bus connection switch circuit to be controlled by the graphic processor to effect a connection control between the first and second address buses and between the first and second data buses so as to enable execution of a drawing processing in the main memory connected to a bus on the main processor side and a data transfer between the main memory and the frame buffer.

    摘要翻译： 一种图形处理系统，包括用于存储程序的主存储器和与像素相对应的信息，用于执行从主存储器或从外部设备传送的程序的执行处理以便控制系统的主处理器，显示/输出设备 例如用于输出通过控制以多个维度排列的像素获得的图形信息的CRT设备和打印机，用于存储对应于输出到显示/输出设备的像素的信息的帧缓冲器，以及用于接收命令和参数的图形处理器 从主存储器和/或主处理器传送的信息，用于根据预定的处理过程产生字符和图形数据，并且用于执行包括执行绘图处理的传送控制，以通过第一和第二地址总线传送生成的数据;以及 第一和第二数据总线到主存储器和/或帧缓冲器， 分别。 该系统还包括由图形处理器控制的总线连接开关电路，以实现第一和第二地址总线之间以及第一和第二数据总线之间的连接控制，以便能够执行连接到 主处理器侧的总线和主存储器与帧缓冲器之间的数据传输。