公开(公告)号：US20080320175A1

公开(公告)日：2008-12-25

申请号：US12199269

申请日：2008-08-27

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/00

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: Apparatus and methods provide for configuring a peripheral device in response to applying defined sets of signals to input/output terminals of the peripheral device, sensing the signals at those input/output terminals after applying the defined sets of signals, and comparing the sensed signals with the defined sets of signals.

Abstract translation: 装置和方法提供用于响应于将定义的信号集合应用于外围设备的输入/输出端子来配置外围设备，在应用所定义的信号集之后感测那些输入/输出端子处的信号，并将感测信号与 定义的信号组。

公开(公告)号：US07421523B2

公开(公告)日：2008-09-02

申请号：US11292496

申请日：2005-12-01

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F13/12

CPC classification number: G11C7/20 ,  G06F13/387 ,  G06F13/4081 ,  G06F2213/0042 ,  G11C7/1045

Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols.

Abstract translation: 一种接口系统，在主计算机系统和闪存卡之间以选定的操作模式促进用户友好的连接。 接口系统包括接口设备和闪存卡。 接口系统具有显着扩展闪存卡内的工作模式检测功能，并显着减少了操作模式的错误检测。 接口设备包括用于耦合到主计算机的第一端和用于耦合到闪存卡的第二端，同时支持主机计算机系统也支持的所选操作模式中的通信。 闪存卡利用五十针连接通过接口设备与主机系统进行接口。 闪存卡的五十针连接可以在各种配置中使用，例如通用串行模式，PCMCIA模式和ATA IDE模式。 这些操作模式中的每一种都需要不同的协议。

公开(公告)号：US20080094886A1

公开(公告)日：2008-04-24

申请号：US11674124

申请日：2007-02-12

Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

IPC: G11C11/14 ,  H01L21/8239

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

Abstract: One embodiment of the present invention includes a non-uniform switching based non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer, wherein switching current is applied, in a direction that is substantially perpendicular to the fixed, barrier, first free, non-uniform and the second free layers causing switching between states of the first, second free and non-uniform layers with substantially reduced switching current.

Abstract translation: 本发明的一个实施例包括：非均匀的基于开关的非易失性磁存储元件，其包括固定层，形成在固定层顶部的阻挡层，形成在阻挡层顶部上的第一自由层， 形成在第一自由层的顶部上的均匀开关层（NSL）和形成在非均匀开关层顶部的第二自由层，其中施加开关电流，其基本上垂直于固定屏障的方向， 第一自由，不均匀和第二自由层引起第一，第二自由和非均匀层的状态之间的切换，其开关电流大大降低。

公开(公告)号：US20070201265A1

公开(公告)日：2007-08-30

申请号：US11678515

申请日：2007-02-23

Applicant: Rajiv Yadav Ranjan ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Mahmud Assar ,  Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/1675 ,  B82Y10/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

Abstract: One embodiment of the present invention includes a multi-state current-switching magnetic memory element having a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

Abstract translation: 本发明的一个实施例包括具有由用于存储多于一位的信息的非磁性层分隔的磁隧道结（MTJ）堆叠的多状态电流切换磁存储元件，其中施加到 存储器元件导致切换到不同的状态。

公开(公告)号：US5818781A

公开(公告)日：1998-10-06

申请号：US748867

申请日：1996-11-13

Applicant: Petro Estakhri ,  Mahmud Assar ,  Boyd Gayle Pett

Inventor： Petro Estakhri ,  Mahmud Assar ,  Boyd Gayle Pett

IPC: G11C16/06 ,  G01R19/165 ,  G06F1/26 ,  G06F11/00 ,  G06K19/07 ,  G11C5/14 ,  G11C16/30

CPC classification number: G06F1/26 ,  G01R19/16538 ,  G06K19/07 ,  G11C16/30 ,  G11C5/143 ,  G06F11/0754

Abstract: A computer card including a voltage detection circuit having Flash EEPROM devices and a controller device, the voltage detection circuit further including a variable voltage detector for determining the system voltage level provided by a power supply within the computer product and appropriately enabling a voltage regulator circuit for dividing the system voltage level to a level suited for operation by the Flash EEPROM devices and applying this operational voltage level to the Flash EEPROM devices. Upon determining the system voltage level provided by the power supply to be appropriately suited for operation of the Flash EEPROM devices, disabling the voltage regulator circuit and providing the system voltage level to the Flash EEPROM devices.

Abstract translation: 一种包括具有闪速EEPROM装置的电压检测电路和控制器装置的计算机卡，所述电压检测电路还包括用于确定由所述计算机产品内的电源提供的系统电压电平的可变电压检测器，并且适当地启用电压调节器电路 将系统电压电平划分为适合Flash EEPROM器件操作的电平，并将该工作电压电平施加到闪存EEPROM器件。 在确定由电源提供的系统电压电平适合于闪存EEPROM器件的操作时，禁用电压调节器电路并向闪存EEPROM器件提供系统电压电平。

公开(公告)号：US5596526A

公开(公告)日：1997-01-21

申请号：US515188

申请日：1995-08-15

Applicant: Mahmud Assar ,  Parviz Keshtbod

Inventor： Mahmud Assar ,  Parviz Keshtbod

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C11/34

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5642

Abstract: A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

Abstract translation: 多级NAND架构非易失性存储器件通过与恒定电流电平进行比较来读取和编程存储器单元，每个存储单元存储多于一位的数据，同时选择性地调整读或编程的单元或单元上的栅极电压。 提供多个读取和写入参考单元，每个编程为对应于多级编程中的每一个，其中在读取存储器单元期间，读取的参考单元提供恒定电流电平，并且在写入存储器单元期间，写入 参考细胞提供相同的。 此外，在读取操作期间，将相应的写入参考单元耦合到读取参考单元以测量与读取存储器单元相关联的读取时间。

公开(公告)号：US5388083A

公开(公告)日：1995-02-07

申请号：US38668

申请日：1993-03-26

Applicant: Mahmud Assar ,  Siamack Nemazie ,  Petro Estakhri

Inventor： Mahmud Assar ,  Siamack Nemazie ,  Petro Estakhri

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C7/00

CPC classification number: G11C16/3495 ,  G06F3/0601 ,  G11C16/102 ,  G11C16/349 ,  G06F2003/0694

Abstract: A semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, all blocks in the mass storage are used evenly. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old version of a block, a count to determine the number of times a block has been erased and written and erase inhibit flag.

Abstract translation: 半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 （擦除周期被理解为包括完全编程要擦除的块，然后擦除块）。通过将更改后的数据文件编程为空的大容量存储块而不是将硬盘自身编程，可以避免擦除周期。 定期地，大容量存储将需要清理。 其次，大容量存储中的所有块均匀使用。 这些优点通过使用几个标志来实现，地图将块的逻辑地址与该块的物理地址和每个块的计数寄存器相关联。 特别地，为缺陷块，使用块，旧版块，用于确定块被擦除的次数和写入和擦除禁止标志的计数提供标志。

公开(公告)号：US08440471B2

公开(公告)日：2013-05-14

申请号：US13345608

申请日：2012-01-06

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud Assar

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud Assar

IPC: H01L21/00 ,  H01L29/82 ,  G01C11/02

CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

Abstract: A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract translation: 闪存RAM存储器的方法包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器 非易失性RAM驻留在单片模具上。 非易失性RAM由以三维形式布置的磁存储单元堆叠形成，用于更高密度和更低成本。

公开(公告)号：US20120107964A1

公开(公告)日：2012-05-03

申请号：US13345608

申请日：2012-01-06

Applicant: Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Mahmud ASSAR

Inventor： Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Mahmud ASSAR

IPC: H01L21/8239

CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

Abstract: A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract translation: 闪存RAM存储器的方法包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器 非易失性RAM驻留在单片芯片上。 非易失性RAM由以三维形式布置的磁存储单元堆叠形成，用于更高密度和更低成本。

公开(公告)号：US20120069649A1

公开(公告)日：2012-03-22

申请号：US13305646

申请日：2011-11-28

Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

IPC: G11C11/14 ,  H01L29/82

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.