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    Protecting layer, composite for forming the same, method of forming the protecting layer, plasma display panel comprising the protecting layer
    11.
    发明申请
    Protecting layer, composite for forming the same, method of forming the protecting layer, plasma display panel comprising the protecting layer 审中-公开
    保护层，用于形成保护层的复合材料，形成保护层的方法，包括保护层的等离子体显示面板

    公开(公告)号：US20060154801A1

    公开(公告)日：2006-07-13

    申请号：US11328107

    申请日：2006-01-10

    Applicant: Min-Suk Lee ,  Jong-Seo Choi ,  Suk-Ki Kim ,  Jae-Hyuk Kim ,  Soon-Sung Suh

    Inventor： Min-Suk Lee ,  Jong-Seo Choi ,  Suk-Ki Kim ,  Jae-Hyuk Kim ,  Soon-Sung Suh

    IPC: C04B35/04 ,  H01J17/00 ,  H01J9/24

    CPC classification number: H01J11/40 ,  C04B35/04 ,  C04B35/653 ,  C04B2235/3272 ,  C04B2235/3275 ,  C04B2235/3279 ,  C04B2235/3281 ,  C04B2235/443 ,  C04B2235/445 ,  C23C30/00 ,  H01J11/12

    Abstract: A protecting layer is formed of a magnesium oxide and at least one additional component selected from the group consisting of a copper component selected from copper and a copper oxide, a nickel component selected from nickel and a nickel oxide, a cobalt component selected from cobalt and a cobalt oxide, and an iron component selected from iron and an iron oxide; a composite for forming the protecting layer; a method of forming the protecting layer; and a plasma display panel including the protecting layer. The protecting layer, which is used in a PDP, protects an electrode and a dielectric layer from a plasma ion generated by a gaseous mixture of Ne and Xe, or He, Ne, and Xe, and discharge delay time and dependency of the discharge delay time on temperature can be decreased and sputtering resistance can be increased.

    Abstract translation: 保护层由氧化镁和至少一种选自铜和氧化铜的铜成分，选自镍和氧化镍的镍成分，选自钴的钴成分和选自钴的钴成分组成的组中， 钴氧化物和选自铁和氧化铁的铁组分; 用于形成保护层的复合材料; 形成保护层的方法; 以及包括保护层的等离子体显示面板。 用于PDP中的保护层保护电极和电介质层免受由Ne和Xe或He，Ne和Xe的气体混合物产生的等离子体离子，并且放电延迟时间和放电延迟的依赖性 可以降低温度时间，并且可以提高溅射电阻。

    Method for fabricating semiconductor device with fine pattern
    12.
    发明授权
    Method for fabricating semiconductor device with fine pattern 有权
    具有精细图案的半导体器件的制造方法

    公开(公告)号：US07074722B2

    公开(公告)日：2006-07-11

    申请号：US10748613

    申请日：2003-12-29

    Applicant: Min-Suk Lee ,  Sung-Kwon Lee

    Inventor： Min-Suk Lee ,  Sung-Kwon Lee

    IPC: H01L21/302

    CPC classification number: H01L21/76897 ,  H01L21/0276 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

    Abstract: The present invention relates to a method for fabricating a semiconductor device with a fine pattern. The method includes the steps of: (a) forming a semiconductor substrate structure including a substrate, a nitride layer for forming a hard mask, a plurality of conductive patterns, an etch stop layer, an inter-layer insulation layer, an anti-reflective coating (ARC) layer and a photoresist pattern; (b) selectively etching the ARC layer and the nitride layer with use of the photoresist pattern as an etch mask to form a hard mask; (c) removing the photoresist pattern and the ARC layer; (d) etching the inter-layer insulation layer disposed between the conductive patterns by using the hard mask as an etch mask to form a contact hole exposing the etch stop layer; (e) removing the etch stop layer formed at a bottom area of the contact hole to expose the substrate; and (f) forming a plug electrically contacted to the exposed substrate, wherein the steps (b) and (d) to (e) proceeds in an in situ condition.

    Abstract translation: 本发明涉及一种具有精细图案的半导体器件的制造方法。 该方法包括以下步骤：（a）形成半导体衬底结构，其包括衬底，用于形成硬掩模的氮化物层，多个导电图案，蚀刻停止层，层间绝缘层，抗反射层 涂层（ARC）层和光致抗蚀剂图案; （b）使用光致抗蚀剂图案作为蚀刻掩模来选择性地蚀刻ARC层和氮化物层以形成硬掩模; （c）去除光致抗蚀剂图案和ARC层; （d）通过使用硬掩模作为蚀刻掩模蚀刻设置在导电图案之间的层间绝缘层，以形成暴露蚀刻停止层的接触孔; （e）去除形成在接触孔的底部区域处的蚀刻停止层，以露出衬底; 和（f）形成与暴露的基底电接触的插塞，其中步骤（b）和（d）至（e）以原位状态进行。

    Method for fabricating semiconductor device capable of preventing damage by wet cleaning process
    13.
    发明授权
    Method for fabricating semiconductor device capable of preventing damage by wet cleaning process 有权
    制造能够防止湿式清洗工艺损坏的半导体装置的方法

    公开(公告)号：US06995056B2

    公开(公告)日：2006-02-07

    申请号：US10880953

    申请日：2004-06-29

    Applicant: Sung-Kwon Lee ,  Min-Suk Lee

    Inventor： Sung-Kwon Lee ,  Min-Suk Lee

    IPC: H01L21/8249 ,  H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L21/76897 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/10855 ,  H01L27/10888

    Abstract: A method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process. The method includes the steps of: forming a plurality of conductive structures on a substrate; forming an etch stop layer and a flowable insulation layer on the plurality of conductive structures subsequently; forming a photoresist pattern on the flowable insulation layer; forming a plurality of contact holes by etching the flowable insulation layer with use of the photoresist pattern as an etch mask, thereby exposing portions of the etch stop layer; forming at least one barrier layer on the contact holes; removing said at least one barrier layer and the etch stop layer disposed at each bottom portion of the contact holes to thereby expose the substrate; and cleaning the contact holes.

    Abstract translation: 一种制造半导体器件的方法，其能够防止层间绝缘层在湿式清洗过程中被损坏。 该方法包括以下步骤：在衬底上形成多个导电结构; 随后在所述多个导电结构上形成蚀刻停止层和可流动的绝缘层; 在可流动绝缘层上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻可流动绝缘层来形成多个接触孔，从而暴露部分蚀刻停止层; 在所述接触孔上形成至少一个阻挡层; 去除设置在接触孔的每个底部处的所述至少一个阻挡层和蚀刻停止层，从而使基板露出; 并清洁接触孔。

    Method for fabricating semiconductor device capable of reducing seam generations
    14.
    发明授权
    Method for fabricating semiconductor device capable of reducing seam generations 失效
    制造半导体器件的方法，能够减少缝合次数

    公开(公告)号：US06784084B2

    公开(公告)日：2004-08-31

    申请号：US10607052

    申请日：2003-06-27

    Applicant: Hyeok Kang ,  Sung-Kwon Lee ,  Min-Suk Lee

    Inventor： Hyeok Kang ,  Sung-Kwon Lee ,  Min-Suk Lee

    IPC: H01L213205

    CPC classification number: H01L21/76897 ,  H01L21/31144 ,  Y10S438/902 ,  Y10S438/906 ,  Y10S438/976

    Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.

    Abstract translation: 本发明涉及一种用于制造半导体器件的方法，该半导体器件能够防止在接触孔的横截面蚀刻轮廓中由绝缘层的负斜率或弓形轮廓现象引起的空隙和接缝现象的发生。 为了达到这个效果，攻击阻挡层或覆盖层另外沉积在包含自对准接触孔的轮廓上，以防止层间绝缘层的底切，这是缝隙世代的主要原因。 此外，攻击阻挡层具有防止层间绝缘层在湿式清洗/蚀刻工艺期间被侵蚀的功能。 最终，可以通过防止接缝世代改善设备特性。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    19.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20130157385A1

    公开(公告)日：2013-06-20

    申请号：US13529306

    申请日：2012-06-21

    Applicant: Bo Kyoung JUNG ,  Min Suk Lee

    Inventor： Bo Kyoung JUNG ,  Min Suk Lee

    IPC: H01L43/12

    CPC classification number: H01L43/12 ,  G11C11/161

    Abstract: A method for fabricating a semiconductor device includes forming a bottom-electrode metal layer over a substrate, planarizing the bottom-electrode metal layer by a first thickness through a chemical mechanical polishing (CMP) process, etching the bottom-electrode metal layer by a second thickness through a wet etching process, forming a plurality of layers of a magnetic tunneling junction (MTJ) element over the bottom-electrode metal layer, forming a top electrode over the plurality of layers, and forming the MTJ element and a bottom electrode by etching the plurality of layers and the bottom-electrode metal layer using the top electrode as an etch mask.

    Abstract translation: 一种制造半导体器件的方法包括在衬底上形成底部电极金属层，通过化学机械抛光（CMP）工艺将底部电极金属层平坦化第一厚度，然后通过第二次蚀刻底部电极金属层 通过湿蚀刻工艺的厚度，在底电极金属层上形成多个磁隧道结（MTJ）层，在多个层上形成顶电极，并通过蚀刻形成MTJ元件和底电极 所述多个层和所述底部电极金属层使用所述顶部电极作为蚀刻掩模。

    METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION DEVICE
    20.
    发明申请
    METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION DEVICE 有权
    用于制造磁性隧道连接装置的方法

    公开(公告)号：US20130034917A1

    公开(公告)日：2013-02-07

    申请号：US13315011

    申请日：2011-12-08

    Applicant: Min Suk LEE

    Inventor： Min Suk LEE

    IPC: H01L43/12

    CPC classification number: H01L43/12 ,  G11C11/161

    Abstract: A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.

    Abstract translation: 一种用于制造半导体器件的方法包括：形成层叠为底层的多个层，MTJ层和顶层，使用蚀刻掩模图案对顶层和MTJ层进行图案化以形成顶层图案;以及 MTJ图案，在MTJ图案的侧壁上形成碳隔离物和顶层图案以保护MTJ图案和顶层图案，并使用碳间隔物和蚀刻掩模图案作为蚀刻掩模将底层图案化， 形成底层图案。

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