公开(公告)号：US20060013035A1

公开(公告)日：2006-01-19

申请号：US10879090

申请日：2004-06-30

Applicant: Steven Hsu ,  Ram Krishnamurthy

Inventor： Steven Hsu ,  Ram Krishnamurthy

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: A memory circuit includes a word line, a data storage circuit including one or more memory cells or sub-cells, and an inverter coupled between the word line and the N memory cells. The inverter inverts a word-line signal input into a read port of the cells or sub-cells. Because the word-line inverter is local to each cell or sub-cell, DC offset is substantially reduced which translates into a reduction in leakage current.

Abstract translation: 存储器电路包括字线，包括一个或多个存储器单元或子单元的数据存储电路，以及耦合在字线和N个存储单元之间的反相器。 逆变器将输入到单元或子单元的读取端口的字线信号反相。 由于字线逆变器对于每个单元或子单元是局部的，所以DC偏移显着减小，这转化为泄漏电流的减小。

公开(公告)号：US20050225459A1

公开(公告)日：2005-10-13

申请号：US10813084

申请日：2004-03-31

Applicant: Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehea Ismail

Inventor： Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehea Ismail

IPC: G06F13/40 ,  H03M5/00

CPC classification number: G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

Abstract translation: 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。

公开(公告)号：US20050125481A1

公开(公告)日：2005-06-09

申请号：US10728127

申请日：2003-12-04

Applicant: Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy ,  Sapumal Wijeratne

Inventor： Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy ,  Sapumal Wijeratne

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/507

CPC classification number: G06F7/507 ,  G06F7/506

Abstract: An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.

Abstract translation: 一个加法器电路包括多个选择器和一个加法器。 选择器为加法器提供多个输入数据位。 每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。 复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。

公开(公告)号：US20050122158A1

公开(公告)日：2005-06-09

申请号：US10732791

申请日：2003-12-09

Applicant: Atila Alvandpour ,  Ram Krishnamurthy

Inventor： Atila Alvandpour ,  Ram Krishnamurthy

IPC: H03K17/16

CPC classification number: H03K17/164

Abstract: A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.

Abstract translation: 具有经历高到低转换的接收信号的第一反相阈值的静态接收机，以及经历低到高转换的接收信号的第二反相阈值，其中第一反转阈值大于第二反转阈值。 一个实施例包括静态接收器，pFET和nFET，其中当在接收器的输入端口处接收到高电平到低电平的转换时，pFET耦合到输入端口，以有助于提高反转阈值， 并且当在输入端口处接收到低电平到高电平的转换时，nFET耦合到输入端口，以便有助于降低反转阈值。 描述和要求保护其他实施例。

公开(公告)号：US20050068814A1

公开(公告)日：2005-03-31

申请号：US10676276

申请日：2003-09-30

Applicant: Bhaskar Chatterjee ,  Steven Hsu ,  Ram Krishnamurthy

Inventor： Bhaskar Chatterjee ,  Steven Hsu ,  Ram Krishnamurthy

IPC: G11C7/12 ,  G11C7/18 ,  G11C29/00

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C2207/104

Abstract: A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file also has decoder circuitry coupled to said keeper circuitry to selectively decouple the driving signal trace from said global bit trace.

Abstract translation: 寄存器文件包括多电平多路复用器输出电路，其耦合到耦合到所述全局位线跟踪和驱动信号迹线的全局位跟踪和保持器电路。 寄存器文件还具有耦合到所述保持器电路的解码器电路，以选择性地将驱动信号迹线与所述全局位线分离。

公开(公告)号：US06765414B2

公开(公告)日：2004-07-20

申请号：US10246377

申请日：2002-09-17

Applicant: Ali Keshavarzi ,  Bhaskar P. Chatterjee ,  Ram Krishnamurthy ,  Manoj Sachdev

Inventor： Ali Keshavarzi ,  Bhaskar P. Chatterjee ,  Ram Krishnamurthy ,  Manoj Sachdev

IPC: H03K19096

CPC classification number: G01R31/2856 ,  G01R31/3016 ,  G01R31/31707 ,  G01R31/318502

Abstract: A technique is described to allow testing of high-speed digital circuits using lower speed testing equipment, to circuits to be placed into a sleep mode, and to allow burn-in testing of digital circuits with minimal overhead in terms of silicon area or performance.

Abstract translation: 一种技术被描述为允许使用较低速度测试设备的高速数字电路，放置在睡眠模式中的电路进行测试，并允许在硅面积或性能方面具有最小开销的数字电路的老化测试。

公开(公告)号：US06628557B2

公开(公告)日：2003-09-30

申请号：US09966193

申请日：2001-09-28

Applicant: Steven K. Hsu ,  Ram Krishnamurthy

Inventor： Steven K. Hsu ,  Ram Krishnamurthy

IPC: G11C700

CPC classification number: G11C7/12 ,  G11C11/419

Abstract: The present invention is in the area of memory architecture. More particularly, the present invention provides a method, apparatus, machine-readable medium, and system reduce leakage current in memory. Embodiments may take advantage of the reverse bias characteristic of circuit elements, such as the reverse gate-to-source bias characteristic of a transistor, within the memory to limit leakage and provide for a leakage tolerant data storage technique. Embodiments may also enable the reverse bias characteristic of circuit elements, such as the reverse gate-to-source bias characteristic of a transistor, to be taken advantage of by sourcing charge from data storage elements.

Abstract translation: 本发明在存储器架构的领域。 更具体地说，本发明提供一种方法，装置，机器可读介质和系统减少存储器中的泄漏电流。 实施例可以利用电路元件的反向偏置特性，例如存储器内的晶体管的反向栅极到源极偏置特性，以限制泄漏并提供泄漏容限数据存储技术。 实施例还可以使电路元件的反向偏置特性（例如晶体管的反向栅极 - 源极偏置特性）被利用来从数据存储元件中提取电荷。

公开(公告)号：US06597623B2

公开(公告)日：2003-07-22

申请号：US09896349

申请日：2001-06-28

Applicant: Ram Krishnamurthy ,  Ganesh Balamurugan

Inventor： Ram Krishnamurthy ,  Ganesh Balamurugan

IPC: G11C800

CPC classification number: G11C8/10 ,  G06F9/30141

Abstract: A low power architecture for register files is provided. A decoder receives a specified bit address divided into a first input and a second input. The decoder is split into a first stage and a second stage. A pre-decoder in the first stage receives the first input, identifies a local bitline that is accessed, and outputs a first signal to a register file array. A post decoder in the second stage receives the second input and the first signal, processes the identification of the local bitline, and generates a second signal to be sent to the register file array. A delay synchronizes the first signal and the second signal so that both signals reach the register file array simultaneously.

Abstract translation: 提供了一种用于注册文件的低功耗架构。 解码器接收分成第一输入和第二输入的指定位地址。 解码器被分成第一阶段和第二阶段。 第一级的预解码器接收第一输入，识别被访问的本地位线，并将第一信号输出到寄存器文件阵列。 第二级的后解码器接收第二输入和第一信号，处理本地位线的识别，并产生要发送到寄存器文件阵列的第二信号。 延迟同步第一信号和第二信号，使得两个信号同时到达寄存器文件阵列。

公开(公告)号：US20190205273A1

公开(公告)日：2019-07-04

申请号：US16146534

申请日：2018-09-28

Applicant: Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

Inventor： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

IPC: G06F13/16 ,  H01L25/18 ,  G11C11/419 ,  G11C11/408 ,  H01L23/522 ,  H03K19/21

Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

公开(公告)号：US20190080731A1

公开(公告)日：2019-03-14

申请号：US16124068

申请日：2018-09-06

Applicant: Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

Inventor： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

IPC: G11C7/10 ,  G11C11/56 ,  G11C7/18

Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.