公开(公告)号：USD622684S1

公开(公告)日：2010-08-31

申请号：US29353808

申请日：2010-01-14

Applicant: Hyung Yuel Kim ,  Jun Ki Kim ,  Sang Gi Kim ,  Mi Sun Park

Designer： Hyung Yuel Kim ,  Jun Ki Kim ,  Sang Gi Kim ,  Mi Sun Park

公开(公告)号：US06774697B2

公开(公告)日：2004-08-10

申请号：US10325929

申请日：2002-12-23

Applicant: Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

Inventor： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

IPC: H03L500

CPC classification number: H03K19/0016

Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.

Abstract translation: 本发明涉及输入和输出端口电路。 输入输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于 选择性地根据功率模式控制信号提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值确定信号的方向，以及输入/输出寄存器的值，输出控制 电路根据控制寄存器的值和信号方向控制电路的输出驱动，以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以使用单个输出驱动电路同时驱动，单输出驱动电路构成多级，由输出控制寄存器有选择地驱动。 因此，可以节省功耗。

公开(公告)号：US06284605B1

公开(公告)日：2001-09-04

申请号：US09428403

申请日：1999-10-28

Applicant: Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

Inventor： Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

IPC: H01L21336

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Abstract translation: 一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于 有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度 在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻 第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。

公开(公告)号：US20190194893A1

公开(公告)日：2019-06-27

申请号：US16327074

申请日：2017-07-25

Applicant: Sang Gi KIM

Inventor： Sang Gi KIM

IPC: E02B3/04 ,  E02D25/00 ,  E02D23/08

CPC classification number: E02B3/04 ,  E02D23/00 ,  E02D23/08 ,  E02D25/00 ,  E02D2250/0061 ,  E02D2600/20

Abstract: A concrete block construction method, including: manufacturing a plurality of concrete blocks each having a vertical guide hole formed in a vertical direction; preparing a guide member for installing the concrete blocks; forming a lower concrete block structure by installing at least one of the concrete blocks; placing the concrete block subject to be installed on the lower concrete block structure by inserting the installation guide pole into the vertical guide hole of the concrete block subject to be installed; and separating and recovering the guide member for installing the concrete block from the concrete block subject to be installed, after placing the concrete block subject to be installed.

公开(公告)号：US20110058764A1

公开(公告)日：2011-03-10

申请号：US12872881

申请日：2010-08-31

Applicant: Gyungock KIM ,  Jeong Woo Park ,  Jongbum You ,  Sang Gi Kim ,  Sanghoon Kim ,  In Gyoo Kim ,  Jiho Joo ,  Duk Jun Kim ,  Dongwoo Suh ,  Sahnggi Park ,  Ki Seok Jang ,  Junghyung Pyo ,  Kap-Joong Kim ,  Do Won Kim ,  Dae Seo Park

Inventor： Gyungock KIM ,  Jeong Woo Park ,  Jongbum You ,  Sang Gi Kim ,  Sanghoon Kim ,  In Gyoo Kim ,  Jiho Joo ,  Duk Jun Kim ,  Dongwoo Suh ,  Sahnggi Park ,  Ki Seok Jang ,  Junghyung Pyo ,  Kap-Joong Kim ,  Do Won Kim ,  Dae Seo Park

IPC: G02F1/035

CPC classification number: G02F1/025 ,  G02F2201/063

Abstract: Provided is an electro-optic modulating device. The electro-optic modulating device includes an optical waveguide with a vertical structure and sidewalls of the vertical structure are used to configure a junction.

Abstract translation: 提供了一种电光调制装置。 电光调制装置包括具有垂直结构的光波导，垂直结构的侧壁用于构造接合部。

公开(公告)号：US07190432B2

公开(公告)日：2007-03-13

申请号：US11249783

申请日：2005-10-13

Applicant: Sang Gi Kim ,  Ju Wook Lee ,  Jong Moon Park ,  Seong Wook Yoo ,  Kun Sik Park ,  Yong Sun Yoon ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Boo Woo Kim

Inventor： Sang Gi Kim ,  Ju Wook Lee ,  Jong Moon Park ,  Seong Wook Yoo ,  Kun Sik Park ,  Yong Sun Yoon ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Boo Woo Kim

IPC: G03B27/32 ,  G03B27/42 ,  G03B27/70 ,  G03B27/54

CPC classification number: G03F7/70425

Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.

Abstract translation: 提供了一种在半导体器件制造工艺中使用的晶片曝光装置，该曝光装置包括：用于反射从光源提供的光的反射镜; 用于改变从反射镜提供的光的路径的光路改变器; 首先将镜子安装在光路改换器的两侧，以改变光线的路径; 第二个镜子安装在材料的两侧以改变光线的路径; 和第三反射镜，其安装在掩模的两侧，以将由第一反射镜反射的光进入掩模，并将通过掩模的光进入第二反射镜，由此可以连续地将一个表面，两个表面或一个 在晶片一次对准的状态下晶片的比表面。

公开(公告)号：US07133954B2

公开(公告)日：2006-11-07

申请号：US10625126

申请日：2003-07-22

Applicant: Yil-suk Yang ,  Jong-dae Kim ,  Tae-moon Roh ,  Dae-woo Lee ,  Sang-gi Kim ,  Il-yong Park ,  Byoung-gon Yu

Inventor： Yil-suk Yang ,  Jong-dae Kim ,  Tae-moon Roh ,  Dae-woo Lee ,  Sang-gi Kim ,  Il-yong Park ,  Byoung-gon Yu

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

Abstract: Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system includes an external access bus used when data is output from the CPU or data is input to the I/O unit or the internal memory unit; an internal access bus used when data is input to the CPU, data is output from the I/O unit or the internal memory unit, or data is input to or output from the peripheral circuitry; and an internal memory test bus used when data is output from the internal memory unit and input to the I/O unit.

Abstract translation: 提供了一种用于微控制器的数据总线系统，其具有输入/输出（I / O）单元，中央处理单元（CPU），内部存储器单元和外围电路。 数据总线系统包括当从CPU输出数据或将数据输入到I / O单元或内部存储器单元时使用的外部存取总线; 当数据输入到CPU时使用的内部访问总线，数据从I / O单元或内部存储器单元输出，或者数据被输入到外围电路或从外围电路输出; 以及当从内部存储器单元输出数据并输入到I / O单元时使用的内部存储器测试总线。

公开(公告)号：US20060079030A1

公开(公告)日：2006-04-13

申请号：US11179983

申请日：2005-07-12

Applicant: Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

Inventor： Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

IPC: H01L21/8232 ,  H01L21/338

CPC classification number: H01L21/28587

Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.

公开(公告)号：US06855581B2

公开(公告)日：2005-02-15

申请号：US10153975

申请日：2002-05-23

Applicant: Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

Inventor： Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

IPC: H01L21/76 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.

Abstract translation: 本发明涉及使用其中绝缘膜和硅层依次层叠在硅衬底上的SOI结构的衬底的高压大功率集成电路器件的制造方法。 该方法包括以下步骤：在硅层上依次形成氧化物膜和光致抗蚀剂膜，然后使用沟槽掩模进行光刻工艺以对光刻胶膜进行图案化; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化膜，然后在图案化之后除去光致抗蚀剂膜; 使用所述图案化氧化膜作为掩模蚀刻所述硅层，直到所述绝缘膜暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜，执行退火处理并在整个表面上沉积多晶硅，使得沟槽被埋置; 并且顺序地去除多晶硅和氮化物膜，直到硅层暴露以使表面变平，从而形成用于在沟槽内的器件之间进行电隔离的器件隔离膜。 因此，本发明能够有效地降低高压大功率器件与逻辑CMOS器件之间的沟槽的隔离面积，能够容易地控制深井的浓度。

公开(公告)号：US06511886B2

公开(公告)日：2003-01-28

申请号：US10032629

申请日：2001-12-26

Applicant: Jong-dae Kim ,  Sang-gi Kim ,  Tae-moon Roh ,  Jin-gun Koo ,  Dae-woo Lee ,  Kyoung-ik Cho

Inventor： Jong-dae Kim ,  Sang-gi Kim ,  Tae-moon Roh ,  Jin-gun Koo ,  Dae-woo Lee ,  Kyoung-ik Cho

IPC: H01L21336

CPC classification number: H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

Abstract: A method for manufacturing a trench-gate type power semiconductor device is provided. A drift region having a low concentration of a first conductivity type and a body region of a second conductivity type are formed on a semiconductor substrate having a high concentration of the first conductivity type. A trench is formed using a nitride layer pattern and a sidewall oxide layer formed at sidewalls of the nitride layer pattern as a mask, and then the sidewall oxide layer is removed. The corners of the trench are rounded by performing a heat treatment in a hydrogen atmosphere. A source region having a high concentration of the first conductivity type is formed using the nitride layer pattern as a mask. The nitride layer pattern is removed, and an upper oxide layer pattern is formed to cover a predetermined portion of the source region and the gate conductive layer. A body contact region of the second conductivity type is formed using the upper oxide layer pattern as a mask. A source electrode is formed to be electrically connected to the body contact region, and a drain electrode is formed to be electrically connected to the semiconductor substrate.

Abstract translation: 提供一种制造沟槽栅型功率半导体器件的方法。 具有第一导电类型的低浓度和第二导电类型的体区的漂移区形成在具有高浓度的第一导电类型的半导体衬底上。 使用形成在氮化物层图案的侧壁处的氮化物层图案和侧壁氧化物层作为掩模形成沟槽，然后去除侧壁氧化物层。 通过在氢气氛中进行热处理，使沟槽的角部变圆。 使用氮化物层图案作为掩模来形成具有高浓度的第一导电类型的源区。 去除氮化物层图案，并且形成上部氧化物层图案以覆盖源极区域和栅极导电层的预定部分。 使用上部氧化物层图案作为掩模形成第二导电类型的体接触区域。 源电极形成为电连接到主体接触区域，并且形成漏电极以与半导体衬底电连接。