公开(公告)号：US20050263891A1

公开(公告)日：2005-12-01

申请号：US11100912

申请日：2005-04-07

Applicant: Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

Inventor： Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76867

Abstract: A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.

Abstract translation: 提供了一种用于半导体器件的镶嵌结构。 在一个实施例中，镶嵌结构包括在通孔上形成的沟槽，其将沟槽电耦合到下面的导电层，使得沟槽具有变化的宽度。 通孔排列有第一阻挡层。 沿着通孔底部的第一阻挡层被去除，使得形成在下面的导电层中的凹陷。 沿着通孔底部形成的凹槽使得较窄沟槽下面的凹陷大于形成在较宽沟槽下方的凹陷。 在另一个实施例中，然后可以在第一阻挡层上形成第二阻挡层。 在该实施例中，导电层的一部分可插入在第一阻挡层和第二阻挡层之间。

公开(公告)号：US06821905B2

公开(公告)日：2004-11-23

申请号：US10209466

申请日：2002-07-30

Applicant: Shing-Chyang Pan ,  Shwang-Ming Jeng ,  Chen-Hua Yu ,  Grace H. Ho

Inventor： Shing-Chyang Pan ,  Shwang-Ming Jeng ,  Chen-Hua Yu ,  Grace H. Ho

IPC: H01L21302

CPC classification number: H01L21/76826 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76807

Abstract: A method for preventing carbon and nitrogen penetration from a deposited overlayer into a dielectric insulating layer to improve a subsequent photolithographic patterning and anisotropic etching process including providing a semiconductor wafer having a process surface including an exposed dielectric insulating layer; and, subjecting the dielectric insulating layer to a hydrogen containing plasma treatment to form a penetration resistance to one of nitrogen containing and carbon containing species.

公开(公告)号：USRE41935E1

公开(公告)日：2010-11-16

申请号：US11655743

申请日：2007-01-19

Applicant: Shing-Chyang Pan ,  Keng-Chu Lin ,  Wen-Chih Chiou ,  Shwang-Ming Jeng

Inventor： Shing-Chyang Pan ,  Keng-Chu Lin ,  Wen-Chih Chiou ,  Shwang-Ming Jeng

IPC: H01L21/26 ,  H01L21/324 ,  H01L21/42 ,  H01L21/4763 ,  H01L21/477

CPC classification number: H01L21/76814 ,  H01L21/3003 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/76807 ,  H01L21/76843

Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.

Abstract translation: 一种用于等离子体处理各向异性蚀刻的开口以改善裂纹起始和传播阻力的方法，包括提供具有包括各向异性蚀刻的开口的半导体晶片，所述工艺表面包括至少部分延伸穿过介电绝缘层的工艺表面; 在至少一个等离子体处理等离子体处理包括各向异性蚀刻的开口的工艺表面，以改善随后沉积的难熔金属粘合/阻挡层在其上的粘附; 并且毯子沉积至少一个难熔金属粘合/阻挡层以对各向异性蚀刻的开口进行排列。

公开(公告)号：US20080199978A1

公开(公告)日：2008-08-21

申请号：US11707662

申请日：2007-02-16

Applicant: Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

Inventor： Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

IPC: G01R31/26

CPC classification number: G01R31/2831 ,  H01L22/12

Abstract: A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.

Abstract translation: 在晶片上形成当前顶层之后测试晶片的方法。 在形成当前顶层之后，为晶片收集应力数据。 应力数据来源于晶片曲率的变化。 应力数据包括：在x方向上的应力x x和在晶片上的一组有限区域的每个区域的ay方向上的应力yy，应力xx和应力yy都源自晶片曲率变化 - x x在x方向上对于有限区域集合中的每个区域以及从y方向的晶片曲率变化yy到该有限区域集合中的每个区域; 并且应力xy从晶片曲率变化xy得到，其中晶片曲率变化xy是在该有限区域的每个区域的x-y平面中的晶片扭转的变化。 应力梯度矢量（和/或其范数）被计算并用于评估调查单个或多个累积层。

公开(公告)号：US07226860B2

公开(公告)日：2007-06-05

申请号：US10833154

申请日：2004-04-28

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC: H01L21/44

CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

公开(公告)号：US07030023B2

公开(公告)日：2006-04-18

申请号：US10655972

申请日：2003-09-04

Applicant: Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

IPC: H01L21/302

CPC classification number: H01L21/3105 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract translation: 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。

公开(公告)号：US20050189075A1

公开(公告)日：2005-09-01

申请号：US10789660

申请日：2004-02-27

Applicant: Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

IPC: B08B7/00 ,  H01J37/32 ,  H01L21/00 ,  C23F1/00

CPC classification number: H01L21/67109 ,  B08B7/0071 ,  H01J37/32862

Abstract: A reactive pre-clean chamber that contains a wafer heating apparatus, such as a high-temperature electrostatic chuck (HTESC), for directly heating a wafer supported on the apparatus during a pre-cleaning process. The wafer heating apparatus is capable of heating the wafer to the optimum temperatures required for a hydrogen plasma reactive pre-clean (RPC) process. Furthermore, degassing and pre-cleaning can be carried out in the same pre-clean chamber. The invention further includes a method of pre-cleaning a wafer using a pre-clean chamber that contains a wafer heating apparatus.

Abstract translation: 一种反应性预清洁室，其包含诸如高温静电卡盘（HTESC）的晶片加热装置，用于在预清洁过程期间直接加热支撑在装置上的晶片。 晶片加热装置能够将晶片加热到氢等离子体反应性预清洁（RPC）工艺所需的最佳温度。 此外，脱气和预清洁可以在相同的预清洁室中进行。 本发明还包括使用包含晶片加热装置的预清洁室预清洁晶片的方法。

公开(公告)号：US20050156316A1

公开(公告)日：2005-07-21

申请号：US11070569

申请日：2005-03-02

Applicant: Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chung-Shi Liu ,  Chen-Hua Yu

Inventor： Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/48 ,  H01L21/31 ,  H01L21/469 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76846 ,  H01L21/2855

Abstract: Within a microelectronic fabrication and a method for fabricating the microelectronic fabrication a barrier layer is formed over a substrate. Within the method and the microelectronic fabrication the barrier layer is formed of a refractory metal nitride barrier material having within its thickness a gradient in nitrogen concentration. The barrier layer has low resistivity and improved electromigration performance.

Abstract translation: 在微电子制造和微电子制造的制造方法中，在衬底上形成阻挡层。 在该方法和微电子制造中，阻挡层由其厚度为氮浓度梯度的难熔金属氮化物阻挡材料形成。 阻挡层具有低电阻率和改善的电迁移性能。

公开(公告)号：US10312107B2

公开(公告)日：2019-06-04

申请号：US13228011

申请日：2011-09-08

Applicant: Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L21/311 ,  H01L21/321 ,  H01L21/768

Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

公开(公告)号：US20130062774A1

公开(公告)日：2013-03-14

申请号：US13228011

申请日：2011-09-08

Applicant: Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/321 ,  H01L21/76811 ,  H01L21/76813

Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

Abstract translation: 一种方法包括在低k电介质层上形成金属硬掩模。 形成金属硬掩模的步骤包括沉积金属硬掩模的子层，并对金属硬掩模的子层进行等离子体处理。 将金属硬掩模图案化以形成开口。 蚀刻低k电介质层以形成沟槽，其中使用金属硬掩模作为蚀刻掩模进行蚀刻步骤。