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    Spin field effect transistor using half metal and method of manufacturing the same
    11.
    发明授权
    Spin field effect transistor using half metal and method of manufacturing the same 有权
    使用半金属的自旋场效应晶体管及其制造方法

    公开(公告)号：US07936028B2

    公开(公告)日：2011-05-03

    申请号：US12081283

    申请日：2008-04-14

    Applicant: Ki-ha Hong ,  Sung-hoon Lee ,  Jong-seob Kim ,  Jai Kwang Shin

    Inventor： Ki-ha Hong ,  Sung-hoon Lee ,  Jong-seob Kim ,  Jai Kwang Shin

    IPC: H01L29/82

    CPC classification number: H01L29/66984 ,  B82Y25/00 ,  H01F1/401 ,  H01F1/404 ,  H01F10/1933 ,  H01F10/1936 ,  H01F10/3254 ,  H01F10/3295 ,  H01L29/82

    Abstract: A spin field effect transistor may include at least one gate electrode, a channel layer, a first stack and a second stack separate from each other on a substrate, wherein the channel layer is formed of a half metal. The half metal may be at least one material selected from the group consisting of chrome oxide (CrO2), magnetite (Fe3O4), a double perovskite structure material, a Heusler alloy, NiMnSb, La(1-x)AxMnO3 (A=Ca, Ba, Sr, x˜0.3), and GaN doped with Cu, and the double perovskite structure material is expressed as a chemical composition of A2BB′O6, and a material corresponding to A is Ca, Sr, or Ba, a material corresponding to B is a 3d orbital transition metal, and a material corresponding to B′ is a 4d orbital transition metal. The 3d orbital transition metal may be Fe or Co, and the 4d orbital transition metal is Mo or Re.

    Abstract translation: 自旋场效应晶体管可以包括在基板上彼此分离的至少一个栅电极，沟道层，第一堆叠和第二堆叠，其中沟道层由半金属形成。 半金属可以是选自氧化铬（CrO 2），磁铁矿（Fe 3 O 4），双钙钛矿结构材料，Heusler合金，NiMnSb，La（1-x）AxMnO 3（A = Ca， Ba，Sr，x〜0.3）和掺杂有Cu的GaN，双钙钛矿结构材料表示为A2BB'O6的化学组成，对应于A的材料为Ca，Sr或Ba，相当于 B是3d轨道过渡金属，对应于B'的材料是4d轨道过渡金属。 3d轨道过渡金属可以是Fe或Co，4d轨道过渡金属是Mo或Re。

    Method of forming a mask pattern
    13.
    发明授权
    Method of forming a mask pattern 失效
    形成掩模图案的方法

    公开(公告)号：US07655573B2

    公开(公告)日：2010-02-02

    申请号：US11751734

    申请日：2007-05-22

    Applicant: Sung Hoon Lee

    Inventor： Sung Hoon Lee

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/0337 ,  H01L21/0338

    Abstract: A method of forming a mask pattern and, more particularly, a method of forming a mask pattern wherein micro patterns having resolutions lower than those of exposure equipment by overcoming the resolutions of the exposure equipment, wherein, a silicon layer is formed over a substrate and is patterned. The patterned silicon layer is oxidized to form the entire surface of the silicon layer to a specific thickness by using an oxide layer. The oxide layer is removed to expose a top surface of the silicon layer. A mask pattern is formed with the remaining oxide layer by removing the silicon layer.

    Abstract translation: 更具体地说，一种形成掩模图案的方法，其中通过克服曝光设备的分辨率，其中分辨率低于曝光设备的分辨率的微图案，其中在衬底上形成硅层， 是图案。 通过使用氧化物层，图案化硅层被氧化以形成硅层的整个表面至特定厚度。 去除氧化物层以暴露硅层的顶表面。 通过去除硅层而形成具有剩余氧化物层的掩模图案。

    Semiconductor Device and Method for Manufacturing the Same
    14.
    发明申请
    Semiconductor Device and Method for Manufacturing the Same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20090212345A1

    公开(公告)日：2009-08-27

    申请号：US12137135

    申请日：2008-06-11

    Applicant: Sung Hoon Lee

    Inventor： Sung Hoon Lee

    IPC: H01L29/00 ,  H01L21/3205

    CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521

    Abstract: Disclosed herein are a semiconductor device and a method for manufacturing the same. A method of manufacturing a semiconductor device includes forming a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer and a gate electrode layer on a semiconductor substrate; patterning the gate electrode layer to expose the second conductive layer; forming a protective layer on a side wall of the gate electrode layer; and etching the exposed second conductive layer, the dielectric layer, and the first conductive layer to form a gate pattern.

    Abstract translation: 本文公开了一种半导体器件及其制造方法。 制造半导体器件的方法包括：在半导体衬底上形成隧道绝缘层，第一导电层，电介质层，第二导电层和栅极电极层; 图案化栅电极层以暴露第二导电层; 在所述栅电极层的侧壁上形成保护层; 以及蚀刻暴露的第二导电层，电介质层和第一导电层以形成栅极图案。

    METHOD AND APPARATUS FOR HIERARCHICAL MODULATION AND DEMODULATION IN DIGITAL BROADCASTING SYSTEM
    15.
    发明申请
    METHOD AND APPARATUS FOR HIERARCHICAL MODULATION AND DEMODULATION IN DIGITAL BROADCASTING SYSTEM 审中-公开
    数字广播系统中分层调制和解调的方法与装置

    公开(公告)号：US20080137775A1

    公开(公告)日：2008-06-12

    申请号：US11931074

    申请日：2007-10-31

    Applicant: Tae Hoon KIM ,  In Ki LEE ,  Seung Hyun CHOI ,  Cheon In OH ,  Dae Ig CHANG ,  Ho Jin LEE ,  Sung Hoon LEE ,  Goon Seop LEE ,  Dong Hahk LEE ,  Jae Hwang YU

    Inventor： Tae Hoon KIM ,  In Ki LEE ,  Seung Hyun CHOI ,  Cheon In OH ,  Dae Ig CHANG ,  Ho Jin LEE ,  Sung Hoon LEE ,  Goon Seop LEE ,  Dong Hahk LEE ,  Jae Hwang YU

    IPC: H04L27/20 ,  H03D3/22 ,  H04L27/22

    CPC classification number: H04L27/183

    Abstract: Provided are a method and apparatus for hierarchical modulation and demodulation in a Digital Multimedia Broadcasting (DMB) system. The method for hierarchical modulation in a digital broadcast signal transmitter includes the steps of: receiving a first broadcast signal and a second broadcast signal from outside, and encoding the broadcast signals by a first method and a second method, respectively; synthesizing the encoded first and second broadcast signals; determining a modulation point using a constellation diagram of an I-Q plane corresponding to the synthesized signal; and hierarchically phase-shift modulating the synthesized signal using the determined modulation point. Here, in the I-Q plane, the modulation point is deviated by a predetermined deviation angle from a phase axis passing through a modulation point of the first broadcast signal and an origin of the I-Q plane.

    Abstract translation: 提供了一种用于数字多媒体广播（DMB）系统中的分级调制和解调的方法和装置。 数字广播信号发射机中的分级调制方法包括以下步骤：从外部接收第一广播信号和第二广播信号，并分别通过第一种方法和第二种方法对广播信号进行编码; 合成编码的第一和第二广播信号; 使用与合成信号对应的I-Q平面的星座图确定调制点; 以及使用所确定的调制点对合成信号进行分层相移。 这里，在I-Q平面中，调制点偏离了通过第一广播信号的调制点的相位轴和I-Q平面的原点的预定偏差角。

    Method of forming isolation film of semiconductor device
    17.
    发明授权
    Method of forming isolation film of semiconductor device 失效
    形成半导体器件隔离膜的方法

    公开(公告)号：US07060630B2

    公开(公告)日：2006-06-13

    申请号：US10628803

    申请日：2003-07-28

    Applicant: Sung Hoon Lee

    Inventor： Sung Hoon Lee

    IPC: H01L21/302

    CPC classification number: H01L21/76205 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/0231 ,  H01L21/3063 ,  H01L21/31662

    Abstract: Disclosed is a method of forming the isolation film in the semiconductor device. The method comprises the steps of sequentially forming a pad oxide film and a pad nitride film on a silicon substrate, forming a photoresist pattern through which an isolation region is opened, on the pad nitride film, etching the pad nitride film and the pad oxide film using the photoresist pattern as an etch mask, thus exposing the silicon substrate of the isolation region, implementing an electrochemical etch process to form porous silicon in the silicon substrate of the exposed isolation region, removing the photoresist pattern, and implementing a thermal oxidization process to oxidize porous silicon, thereby forming an oxide film in the isolation region.

    Abstract translation: 公开了一种在半导体器件中形成隔离膜的方法。 该方法包括以下步骤：在硅衬底上依次形成衬垫氧化膜和衬垫氮化物膜，在衬垫氮化物膜上形成隔离区打开的光致抗蚀剂图案，蚀刻衬垫氮化物膜和衬垫氧化膜 使用光致抗蚀剂图案作为蚀刻掩模，从而暴露隔离区域的硅衬底，实现电化学蚀刻工艺以在暴露的隔离区域的硅衬底中形成多孔硅，去除光致抗蚀剂图案，并实施热氧化过程 氧化多孔硅，从而在隔离区中形成氧化膜。

    Gate structure in flash memory cell and method of forming the same, and method of forming dielectric film
    18.
    发明授权
    Gate structure in flash memory cell and method of forming the same, and method of forming dielectric film 失效
    闪存单元中的栅极结构及其形成方法以及形成介电膜的方法

    公开(公告)号：US07057227B2

    公开(公告)日：2006-06-06

    申请号：US10315253

    申请日：2002-12-10

    Applicant: Sung Hoon Lee

    Inventor： Sung Hoon Lee

    IPC: H01L29/76

    CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

    Abstract: The present invention relates to a gate structure of a flash memory cell and method of forming the same, and method of forming a dielectric film. The method of forming the dielectric film in the flash memory cell comprises the steps of preparing a wafer including a tunnel oxide film formed in a given region of a semiconductor substrate, a polysilicon film formed on the tunnel oxide film, and an oxide film and a silicon nitride film formed on the polysilicon film; preparing a work cell in which a voltage is applied to the rear side of the semiconductor substrate used as a work electrode in which the silicon nitride film is formed, a relative electrode and a reference electrode are kept by a given distance so that they can be immersed in electrolyte, and in which an ultraviolet rays source is formed on an upper side to illuminate an ultraviolet rays to a work electrode; and performing electro-chemical etch using silicon dissociation reaction for the wafer mounted on the work cell to form porosities in the silicon nitride film.

    Abstract translation: 本发明涉及闪存单元的栅极结构及其形成方法，以及形成电介质膜的方法。 在闪速存储单元中形成电介质膜的方法包括以下步骤：制备包括在半导体衬底的给定区域中形成的隧道氧化物膜的晶片，形成在隧道氧化物膜上的多晶硅膜，以及氧化物膜和 形成在多晶硅膜上的氮化硅膜; 准备在用作形成氮化硅膜的工作电极的半导体衬底的后侧施加电压的工作单元，相对电极和参考电极保持给定距离，使得它们可以是 浸入电解质中，并且在上侧形成紫外线源以向工作电极照射紫外线; 以及使用硅解离反应对安装在工作单元上的晶片进行电化学蚀刻，以在氮化硅膜中形成孔隙率。

    Method of forming an isolation film in a semiconductor device
    19.
    发明授权
    Method of forming an isolation film in a semiconductor device 失效
    在半导体器件中形成隔离膜的方法

    公开(公告)号：US07018931B2

    公开(公告)日：2006-03-28

    申请号：US10631238

    申请日：2003-07-31

    Applicant: Sung Hoon Lee

    Inventor： Sung Hoon Lee

    IPC: H01L21/302

    CPC classification number: H01L21/31116 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76232

    Abstract: Disclosed is a method of forming an isolation film in a semiconductor device. In the process of forming a stack structure of a pad oxide film and a pad nitride film that expose a semiconductor substrate in an isolation region, protrusions of a tail profile are formed at the bottom sidewalls of the pad nitride film and the pad oxide film adjacent to the surface of the substrate, and top corners of a trench are made rounded using the protrusions as an anti-etch film when the substrate is etched, Therefore, it is possible to prevent concentration of an electric field on the top corners of the trench and prohibit generation of the leakage current. Accordingly, reliability of the process and electrical characteristics of the device could be improved.

    Abstract translation: 公开了一种在半导体器件中形成隔离膜的方法。 在形成衬垫氧化膜的叠层结构和在隔离区域中露出半导体衬底的衬垫氮化物膜的过程中，在衬垫氮化物膜的底部侧壁和相邻的衬垫氧化膜形成尾部轮廓的突起 在衬底的表面上，并且当蚀刻衬底时，使用突起作为抗蚀刻膜，使沟槽的顶角变圆，因此，可以防止沟槽的顶角上的电场集中 并且禁止产生漏电流。 因此，可以提高工艺的可靠性和装置的电气特性。

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