中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

33 records (took 0.018 seconds)

    Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same
    11.
    发明申请
    Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same 有权
    具有垂直排列的存储器单元串的集成电路存储器件及其操作方法相同

    公开(公告)号：US20100002516A1

    公开(公告)日：2010-01-07

    申请号：US12492209

    申请日：2009-06-26

    Applicant: Jae-Sung Sim ,  Jung-Dal Choi

    Inventor： Jae-Sung Sim ,  Jung-Dal Choi

    IPC: G11C16/04 ,  H01L27/088 ,  H01L21/336

    CPC classification number: H01L27/11551 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

    Abstract: Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors.

    Abstract translation: 非易失性存储器件包括第一NAND型EEPROM单元串，其具有在串中串联电连接的第一多个串选择晶体管。 该第一多个串选择晶体管包括第一多个耗尽型晶体管和第一增强型晶体管。 EEPROM单元的第二NAND型串还在其中设置有串联电连接的第二多个串选择晶体管。 第二多个串选择晶体管包括第二多个耗尽型晶体管和第二增强型晶体管。 根据本发明的这些实施例，第一增强型晶体管相对于第二多个耗尽型晶体管中的一个垂直堆叠，并且第二增强型晶体管相对于第一多个耗尽型晶体管之一垂直堆叠 晶体管。 第一串选择插头被配置为将第一增强型晶体管的栅极电连接到第二多个耗尽型晶体管之一的栅电极。 类似地，第二串选择插头被配置为将第二增强型晶体管的栅电极电连接到第一多个耗尽型晶体管之一的栅电极。

    Integrated circuit memory devices having vertically arranged strings of memory cells therein and methods of operating same
    14.
    发明授权
    Integrated circuit memory devices having vertically arranged strings of memory cells therein and methods of operating same 有权
    具有垂直排列的存储器单元串的集成电路存储器件及其操作方法

    公开(公告)号：US08588001B2

    公开(公告)日：2013-11-19

    申请号：US13181037

    申请日：2011-07-12

    Applicant: Jae-Sung Sim ,  Jung-Dal Choi

    Inventor： Jae-Sung Sim ,  Jung-Dal Choi

    IPC: G11C16/04

    CPC classification number: H01L27/11551 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

    Abstract: Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. The first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect gate electrodes of the first enhancement-mode transistor and one of the second plurality of depletion-mode transistors.

    Abstract translation: 非易失性存储器件包括第一NAND型EEPROM单元串，其具有在串中串联电连接的第一多个串选择晶体管。 该第一多个串选择晶体管包括第一多个耗尽型晶体管和第一增强型晶体管。 EEPROM单元的第二NAND型串提供有串联电连接的第二多个串选择晶体管。 第二多个串选择晶体管包括第二多个耗尽型晶体管和第二增强型晶体管。 第一增强型晶体管相对于第二多个耗尽型晶体管中的一个垂直堆叠，并且第二增强型晶体管相对于第一多个耗尽型晶体管之一垂直堆叠。 第一串选择插头被配置为电连接第一增强型晶体管的栅极和第二多个耗尽型晶体管中的一个。

    Integrated circuit memory devices having vertically arranged strings of memory cells therein and methods of operating same
    15.
    发明授权
    Integrated circuit memory devices having vertically arranged strings of memory cells therein and methods of operating same 有权
    具有垂直排列的存储器单元串的集成电路存储器件及其操作方法

    公开(公告)号：US08004893B2

    公开(公告)日：2011-08-23

    申请号：US12492209

    申请日：2009-06-26

    Applicant: Jae-Sung Sim ,  Jung-Dal Choi

    Inventor： Jae-Sung Sim ,  Jung-Dal Choi

    IPC: G11C16/04

    CPC classification number: H01L27/11551 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

    Abstract: Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors.

    Abstract translation: 非易失性存储器件包括第一NAND型EEPROM单元串，其具有在串中串联电连接的第一多个串选择晶体管。 该第一多个串选择晶体管包括第一多个耗尽型晶体管和第一增强型晶体管。 EEPROM单元的第二NAND型串还在其中设置有串联电连接的第二多个串选择晶体管。 第二多个串选择晶体管包括第二多个耗尽型晶体管和第二增强型晶体管。 根据本发明的这些实施例，第一增强型晶体管相对于第二多个耗尽型晶体管中的一个垂直堆叠，并且第二增强型晶体管相对于第一多个耗尽型晶体管之一垂直堆叠 晶体管。 第一串选择插头被配置为将第一增强型晶体管的栅极电连接到第二多个耗尽型晶体管之一的栅电极。 类似地，第二串选择插头被配置为将第二增强型晶体管的栅电极电连接到第一多个耗尽型晶体管之一的栅电极。

    Methods of forming charge-trap type non-volatile memory devices
    16.
    发明授权
    Methods of forming charge-trap type non-volatile memory devices 有权
    形成电荷陷阱型非易失性存储器件的方法

    公开(公告)号：US07888219B2

    公开(公告)日：2011-02-15

    申请号：US12766272

    申请日：2010-04-23

    Applicant: Jae-Sung Sim ,  Jung-Dal Choi ,  Chang-Seok Kang

    Inventor： Jae-Sung Sim ,  Jung-Dal Choi ,  Chang-Seok Kang

    IPC: H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    Abstract: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.

    Abstract translation: 形成非易失性存储器件的方法可以包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成电荷捕获层。 然后可以形成延伸穿过隧道绝缘层和电荷陷阱层并进入半导体衬底的沟槽，使得电荷陷阱层和隧道绝缘层的部分保留在沟槽的相对侧上。 可以在沟槽中形成器件隔离层，并且可以在器件隔离层上和电荷陷阱层的剩余部分上形成阻挡绝缘层。 可以在阻挡绝缘层上形成栅电极，并且可以对阻挡绝缘层和电荷陷阱层的剩余部分进行图案化以在栅电极和半导体衬底之间提供阻挡绝缘图案和电荷陷阱图案。

    MEMORY DEVICES INCLUDING VERTICAL PILLARS AND METHODS OF MANUFACTURING AND OPERATING THE SAME
    17.
    发明申请
    MEMORY DEVICES INCLUDING VERTICAL PILLARS AND METHODS OF MANUFACTURING AND OPERATING THE SAME 有权
    包括垂直支柱的记忆装置及其制造和操作方法

    公开(公告)号：US20090310425A1

    公开(公告)日：2009-12-17

    申请号：US12471975

    申请日：2009-05-26

    Applicant: Jae-Sung Sim ,  Jung-Dal Choi

    Inventor： Jae-Sung Sim ,  Jung-Dal Choi

    IPC: G11C16/04 ,  H01L29/788 ,  H01L21/336

    CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L21/823481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66666 ,  H01L29/7881

    Abstract: In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

    Abstract translation: 在半导体器件和形成这种器件的方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。 在基板上设置多个层间电介质层。 提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间介电层之间。 半导体材料的垂直沟道沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案，每个栅极图案和垂直沟道之间的栅极绝缘层将栅极图案与垂直沟道绝缘，垂直沟道 在包括半导体区域的接触区域处与衬底接触。

    Heating apparatus using electromagnetic wave
    18.
    发明申请
    Heating apparatus using electromagnetic wave 有权

    公开(公告)号：US20070039953A1

    公开(公告)日：2007-02-22

    申请号：US11267181

    申请日：2005-11-07

    Applicant: Eung Kim ,  Jin Hu ,  Sung Sim

    Inventor： Eung Kim ,  Jin Hu ,  Sung Sim

    IPC: H05B6/76

    CPC classification number: H05B6/763

    Abstract: A heating apparatus using an electromagnetic wave is disclosed, by which cut-of performance of an electromagnetic wave is enhanced by increasing an electromagnetic wave absorption bandwidth having cut-off performance below −70 dB. The present invention includes a door provided to an open front side of a body to be opened/closed, a choke filter having a panel type choke part arranged by at least one or more rows along an edge of the door and a filter part arranged by at least one or more rows along the choke and having a plurality of slots wherein a prescribed choke part is provided to a most inner side, a glass panel attached to an inner lateral side of the door and the choke filter, and a flange part provided to an external end portion of the door along the edge of the door to lie in a same level with an inner lateral side of the glass panel.

    Motion estimation method
    19.
    发明授权
    Motion estimation method 失效
    运动估计法

    公开(公告)号：US06912296B2

    公开(公告)日：2005-06-28

    申请号：US09783330

    申请日：2001-02-15

    Applicant: Woo-sung Sim

    Inventor： Woo-sung Sim

    IPC: H04N19/51 ,  G06K9/00 ,  H04N5/14 ,  H04N7/12 ,  H04N11/02 ,  H04N11/04

    CPC classification number: H04N19/533

    Abstract: A motion estimation method is provided. In the method, respective mean difference values for a current search point within a search block and neighboring search points within the search block are calculated. Then, motion estimation is performed around the current search point if the mean difference value of the current search point is smaller than the mean difference values of the neighboring search points. On the other hand, motion estimation is performed based on the mean difference values of at least some of the neighboring search points if the mean difference value of the current search point is not smaller than the mean difference values of at least one the neighboring search points. The motion estimation method of the present invention does not deteriorate the quality of pictures during image compression in contrast to conventional motion estimation methods and enhances image compression speed by reducing remarkably computational complexity.

    Abstract translation: 提供了运动估计方法。 在该方法中，计算搜索块内的当前搜索点和搜索块内的相邻搜索点的各自的平均差值。 然后，如果当前搜索点的平均差值小于相邻搜索点的平均差值，则在当前搜索点周围执行运动估计。 另一方面，如果当前搜索点的平均差值不小于至少一个相邻搜索点的平均差值，则基于至少一些相邻搜索点的平均差值来执行运动估计 。 与传统的运动估计方法相比，本发明的运动估计方法不会降低图像压缩期间的图像质量，并且通过减少显着的计算复杂度来提高图像压缩速度。

Patent Agency Ranking