利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

52 条记录 (耗时 0.03 秒)

    Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line
    11.
    发明授权
    Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line 有权
    具有芯片间连接单元的堆叠存储器件，包括其的存储器系统以及补偿传输线路的延迟时间的方法

    公开(公告)号：US08929118B2

    公开(公告)日：2015-01-06

    申请号：US13080061

    申请日：2011-04-05

    申请人： Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    发明人： Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C7/10

    CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C7/1048

    摘要： A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

    摘要翻译： 提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号 传输线。 层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元 电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

    Bad page management in memory device or system
    12.
    发明授权
    Bad page management in memory device or system 有权
    内存设备或系统中的页面错误管理

    公开(公告)号：US08769356B2

    公开(公告)日：2014-07-01

    申请号：US13570568

    申请日：2012-08-09

    申请人： Hak-Soo Yu ,  Chul-Woo Park ,  Uk-Song Kang ,  Joo-Sun Choi ,  Hong-Sun Hwang ,  Jong-Pil Son

    发明人： Hak-Soo Yu ,  Chul-Woo Park ,  Uk-Song Kang ,  Joo-Sun Choi ,  Hong-Sun Hwang ,  Jong-Pil Son

    IPC分类号： G11C29/00 ,  G11C29/24

    CPC分类号： G11C29/24 ,  G11C29/00 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

    摘要： A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

    摘要翻译： 存储器件包括存储单元阵列和坏页映射。 存储单元阵列包括以页和列排列的多个存储单元，其中存储单元阵列被划分为与存储单元阵列对应的第一存储块和第二存储块。 坏页面映射存储指示第一存储器块的每个页面是好是坏的页面位置信息。 根据坏页位置信息，第一存储块的失败页地址被第二存储块的通过页地址替换。

    SEMICONDUCTOR DEVICES WITH THROUGH-SILICON VIAS
    16.
    发明申请
    SEMICONDUCTOR DEVICES WITH THROUGH-SILICON VIAS 审中-公开
    半导体器件与硅橡胶

    公开(公告)号：US20110298130A1

    公开(公告)日：2011-12-08

    申请号：US13093439

    申请日：2011-04-25

    申请人： Uk-song Kang

    发明人： Uk-song Kang

    IPC分类号： H01L23/48 ,  H01L23/498

    CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/01055

    摘要： Through silicon vias (TSVs) include a first metal plug having a cylindrical shape, passing through a semiconductor substrate, and with an outer peripheral surface surrounded by a first insulating film; an isolated semiconductor substrate in the semiconductor substrate and surrounding a first metal plug surrounded by a first insulating film; and a second metal plug surrounding the isolated semiconductor substrate and being surrounded by a second insulating film. A first bias voltage is applied to the isolated semiconductor substrate so that a depletion layer is formed in the isolated semiconductor substrate from an interface between the isolated semiconductor substrate and the first insulating film. The first bias voltage is different from a second bias voltage applied to the semiconductor substrate, which is a main semiconductor substrate, with a device forming area where transistors constituting circuits are formed.

    摘要翻译： 通过硅通孔（TSV）包括通过半导体衬底的圆筒形状的第一金属插塞和由第一绝缘膜包围的外周表面; 半导体衬底中的隔离半导体衬底，并围绕由第一绝缘膜包围的第一金属插塞; 以及围绕隔离半导体衬底并被第二绝缘膜包围的第二金属插塞。 第一偏置电压施加到隔离半导体衬底，使得在隔离半导体衬底中从隔离半导体衬底和第一绝缘膜之间的界面形成耗尽层。 第一偏置电压与施加到作为主半导体衬底的半导体衬底的第二偏置电压不同，其中形成有构成电路的晶体管的器件形成区域。

    DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF
    18.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF 审中-公开
    动态随机访问存储器件及其确定周期的方法

    公开(公告)号：US20110122716A1

    公开(公告)日：2011-05-26

    申请号：US13015833

    申请日：2011-01-28

    申请人： Suk-Soo PYO ,  Uk-Song KANG

    发明人： Suk-Soo PYO ,  Uk-Song KANG

    IPC分类号： G11C29/42

    CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/408 ,  G11C2207/104 ,  G11C2211/4061

    摘要： Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.

    摘要翻译： 提供了具有降低的功耗的动态随机存取存储器件以及确定动态随机存取存储器件的刷新周期的方法。 该方法包括：在第一至第n自刷新周期期间选择一个或多个监视位，其中“n”是等于或大于1的自然数; 检测在第（n + 1）至第m自刷新周期期间监视比特是否具有错误，其中“m”是等于或大于n + 1的自然数; 以及根据监视位是否具有错误来调整第（m + 1）个自刷新周期。

    Integrated circuit devices generating a plurality of drowsy clock signals having different phases
    19.
    发明授权
    Integrated circuit devices generating a plurality of drowsy clock signals having different phases 有权
    产生具有不同相位的多个困倦时钟信号的集成电路装置

    公开(公告)号：US07567109B2

    公开(公告)日：2009-07-28

    申请号：US11653864

    申请日：2007-01-17

    申请人： Uk-Song Kang

    发明人： Uk-Song Kang

    IPC分类号： G06F1/04

    CPC分类号： G06F1/08 ,  G01R31/31727 ,  H03K5/00006 ,  H03K5/15033

    摘要： An integrated circuit device which internally generates a plurality of drowsy clock signals having different phases is provided. The integrated circuit device includes a phase synchronizer configured to output a plurality of clock signals having different phases in response to an external clock signal and a drowsy clock signal output unit configured to divide frequencies of the plurality of clock signals by a first factor, align the frequency-divided clock signals so that each consecutive clock signal has a constant phase difference relative to a phase difference of a preceding clock signal, and output the drowsy clock signals having lower frequencies and different phases. The integrated circuit device also includes a feedback unit configured to divide frequency of a clock signal with a phase angle of 0 output by the phase synchronizer by the first factor and output the frequency-divided clock signal having a phase angle of 0 degrees to an input port of the phase synchronizer.

    摘要翻译： 提供了内部生成具有不同相位的多个昏昏欲睡时钟信号的集成电路装置。 集成电路装置包括相位同步器，其被配置为响应于外部时钟信号输出具有不同相位的多个时钟信号，以及昏睡时钟信号输出单元，其被配置为将多个时钟信号的频率除以第一因子， 分频时钟信号，使得每个连续的时钟信号相对于前一时钟信号的相位差具有恒定的相位差，并且输出具有较低频率和不同相位的困倦时钟信号。 集成电路装置还包括反馈单元，其被配置为将由相位同步器输出的相位角0的时钟信号的频率除以第一因子，并将具有0度的相位角的分频时钟信号输出到输入 相位同步器的端口。

    Parallel bit test circuit and method
    20.
    发明授权
    Parallel bit test circuit and method 有权
    并行位测试电路及方法

    公开(公告)号：US07518937B2

    公开(公告)日：2009-04-14

    申请号：US11896828

    申请日：2007-09-06

    申请人： Uk-Song Kang

    发明人： Uk-Song Kang

    IPC分类号： G11C11/00

    CPC分类号： G11C29/34 ,  G11C11/41 ,  G11C2029/1204 ,  G11C2029/2602

    摘要： A parallel bit test circuit for a semiconductor memory device may include a plurality of data compressors, a delay unit, and a bus width converter. The data compressors may receive data output from data lines, compress the data, and output the compressed data. The delay unit may receive a clock signal, and may generate (N−1) number of delayed clock signals from the clock signal when a burst length is a natural number equal to or more than 2. The bus width converter may receive the compressed data through M number of input terminals, divide the compressed data into N number of data sets, and serially output the N number of data sets through M/N number of output terminals in response to the clock signal and the (N−1) number of delayed clock signals, where M may be the number of bits of the data output from the data lines.

    摘要翻译： 用于半导体存储器件的并行位测试电路可以包括多个数据压缩器，延迟单元和总线宽度转换器。 数据压缩器可以接收从数据线输出的数据，压缩数据并输出压缩数据。 延迟单元可以接收时钟信号，并且当突发长度是等于或大于2的自然数时，可以从时钟信号产生（N-1）个延迟时钟信号。总线宽度转换器可以接收压缩数据 通过M个输入端子，将压缩数据分割为N个数据组，并且响应于时钟信号而通过M / N个输出端子串行输出N个数据集，并且（N-1）个数 延迟时钟信号，其中M可以是从数据线输出的数据的位数。