公开(公告)号：US4868422A

公开(公告)日：1989-09-19

申请号：US130815

申请日：1987-12-09

申请人： Vincenzo Daniele ,  Mirella Benedetti

发明人： Vincenzo Daniele ,  Mirella Benedetti

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0948

CPC分类号： H03K19/0948 ,  H03K19/0005 ,  H03K19/01707

摘要： CMOS logic circuit with one or more inputs has at least a complementary pair of transistors, the N-channel driver transistor having a gate directly connected to an input while the P-channel load transistor having a gate connected to the output of the second one of two inverters connected in cascade, the input of the first inverter being connected to the input of the circuit. Using two signal inverting stages or inverters for mirroring the input signal on the gate of the load P-channel transistor of the circuit pair permits the defining of the triggering threshold of the circuit with great freedom, the obtaining of a greater switching speed and the reduction of power dissipation under stand-by conditions. The invention is particularly suited for HCT circuits.

摘要翻译： 具有一个或多个输入的CMOS逻辑电路具有至少一对互补晶体管，所述N沟道驱动晶体管具有与输入端直接连接的栅极，而P沟道负载晶体管具有与第二个晶体管的输出端连接的栅极 两个串联连接的逆变器，第一反相器的输入端连接到电路的输入端。 使用两个信号反相级或反相器来反映电路对的负载P沟道晶体管的栅极上的输入信号，可以大大自由地定义电路的触发阈值，获得更大的开关速度和降低 在待机条件下的功耗。 本发明特别适用于HCT电路。

公开(公告)号：US4357685A

公开(公告)日：1982-11-02

申请号：US168562

申请日：1980-07-14

申请人： Vincenzo Daniele ,  Giuseppe Corda ,  Aldo Magrucci ,  Guido Torelli

发明人： Vincenzo Daniele ,  Giuseppe Corda ,  Aldo Magrucci ,  Guido Torelli

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/32 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L29/7885 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/32 ,  H01L27/115

摘要： A nonvolatile memory of the electrically alterable kind comprises an orthogonal array of cells each including a floating-gate IGFET and an enhancement IGFET in series. For the programming or the reading of a selected cell, lying at the intersection of a row and a column of the array, a common gate lead for all the enhancement IGFETs of the row and a common drain lead for all the enhancement IGFETs of the column are energized with voltage dependent on the desired kind of operation. To write a bit in a cell, its floating gate is progressively charged in a succession of steps separated by reading operations to check on the conduction threshold of the cell; the charging ends when that threshold reaches a predetermined storage level. To cancel a written bit, the floating gate is progressively discharged in a succession of steps again separated by reading operations; the discharging is terminated when the conduction threshold reaches a predetermined cancellation level. The width and/or the amplitude of a voltage pulse applied to an accessible gate of the floating-gate IGFET during the successive charging or discharging steps may be increased after each reading step in which the desired level is not attained.

摘要翻译： 电可变类型的非易失性存储器包括每个包括浮栅IGFET和增强IGFET串联的单元的正交阵列。 对于位于阵列的行和列的交叉点处的选定单元的编程或读取，用于该行的所有增强型IGFET的公共栅极引线和用于该列的所有增强型IGFET的公共漏极引线 根据所需的操作类型而被电压通电。 为了在单元中写入一位，其浮动栅逐步地通过读取操作分离的步骤进行充电，以检查单元的导通阈值; 当该阈值达到预定的存储水平时，充电结束。 为了取消写入位，浮动栅逐步地通过读取操作分开地逐步排出; 当导通阈值达到预定的取消水平时，放电终止。 在连续充电或放电步骤中施加到浮栅IGFET的可访问栅极的电压脉冲的宽度和/或幅度可以在其中未达到期望水平的每个读取步骤之后增加。

公开(公告)号：US4315239A

公开(公告)日：1982-02-09

申请号：US177595

申请日：1980-08-13

申请人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

发明人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

IPC分类号： H01C17/24 ,  H01L21/02 ,  H01L21/033 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01C1/02

CPC分类号： H01L28/20 ,  H01L21/033 ,  Y10T29/49082 ,  Y10T29/49099

摘要： Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.

摘要翻译： 预定电阻率的丝状元素，例如 通过首先在诸如硅体的半导体衬底上沉积介电材料层（例如SiO 2）形成电可编程只读存储器的选择性可破坏的引线，并用导电或非导电涂层将该层顶起来，该导电或非导电涂层对 化学物质如能够侵蚀电介质层的氢氟酸。 接下来，通过光刻处理部分地破坏顶部涂层以留下至少一个基本上矩形的贴片。 此后，电介质层被上述化学物质各向同性地侵蚀，从而将其降低到其原始厚度的大约一半，并且该层的贴片支撑基座的同时横向侵蚀，从而在该基座的周边周围形成大致半圆柱形凹陷的通道。 如果由导电材料或半导体材料组成，则贴片被覆在绝缘包层中，由介电层和贴片用可掺杂多晶硅或金属的所需电导率的沉积物覆盖。 最后，通过化学或离子蚀刻除去基座的通道以及邻接相对的基座侧的一对平行条，除去这些沉积物，由此这些条通过留在另外两边的底切部中的丝状插入物而保持电互连。

公开(公告)号：USRE38166E1

公开(公告)日：2003-07-01

申请号：US09410164

申请日：1999-09-30

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C1156

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m−2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.

摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。

公开(公告)号：US5412599A

公开(公告)日：1995-05-02

申请号：US951274

申请日：1992-09-25

申请人： Vincenzo Daniele ,  Mirella Benedetti ,  Nuccio Villa

发明人： Vincenzo Daniele ,  Mirella Benedetti ,  Nuccio Villa

IPC分类号： H03K17/00 ,  H03K17/62 ,  H03K17/687 ,  H03K17/693 ,  G11C7/02 ,  H03K19/096

CPC分类号： H03K17/6235 ,  H03K17/6872 ,  H03K17/693 ,  H03K2217/0036

摘要： A null consumption CMOS switch which may be set by nonvolatile programming is formed by a pair of complementary transistors preferably having a common drain and a common gate. The common gate is coupled to the floating gate a programmable and erasable, nonvolatile memory cell. The common gate/floating gate coupling can be a unitary floating gate structure. The floating gate directly drives the ON or OFF states of the two complementary transistors. On an output node of the switch, represented by the common drain of the pair of transistors, a signal present on a source node of one or the other of the two complementary transistors is replicated. The state of charge of the floating gate, imposed by programming or erasing, may be such as to reach advantageously a potential higher than the supply voltage or lower than the ground potential of the circuit. Different embodiments, such as a polarity selection, a path selector, a TRISTATE selector, and a logic gate selector are described.

摘要翻译： 可以由非易失性编程设置的零消耗CMOS开关由优选具有公共漏极和公共栅极的一对互补晶体管形成。 公共栅极耦合到浮动栅极可编程和可擦除的非易失性存储单元。 公共栅极/浮动栅极耦合可以是单一的浮动栅极结构。 浮栅直接驱动两个互补晶体管的导通或截止状态。 在由一对晶体管的公共漏极表示的开关的输出节点上，复制存在于两个互补晶体管中的一个或另一个的源极节点上的信号。 通过编程或擦除施加的浮动栅极的充电状态可以有利地达到高于电源电压或低于电路的地电位的电位。 描述了诸如极性选择，路径选择器，TRISTATE选择器和逻辑门选择器的不同实施例。

公开(公告)号：US4631485A

公开(公告)日：1986-12-23

申请号：US687739

申请日：1984-12-28

申请人： Guido Torelli ,  Vincenzo Daniele

发明人： Guido Torelli ,  Vincenzo Daniele

IPC分类号： H03D1/22 ,  H03D1/06

CPC分类号： H03D1/2245

摘要： Two circuits carry out the beating of a modulated signal, with first and second signals, respectively, each having substantially the same frequency as the carrier of the modulated signal but phased-shifted relative to one another by 90.degree.. A commutator controlled by a control circuit alternately selects the signals resulting from the beating. The selection is responsive to the amplitudes of the signals in order to avoid losses of information due to amplitude peaks under a prefixed threshold which may be caused by frequency differences between the signals which are beat.

摘要翻译： 两个电路执行调制信号的跳动，第一和第二信号分别具有与调制信号的载波基本相同的频率，但相对于彼此相位相差90°。 由控制电路控制的换向器交替地选择由跳动产生的信号。 该选择响应于信号的振幅，以便避免由于可能由拍频信号之间的频率差引起的前缀阈值下的振幅峰值引起的信息损失。